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Tue, 03 Feb 2015 23:13:42 +0800 (CST) From: Yakir Yang To: David Airlie , Russell King , Philipp Zabel Date: Tue, 3 Feb 2015 10:13:07 -0500 Message-Id: <1422976387-30165-1-git-send-email-ykk@rock-chips.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1422975418-13302-1-git-send-email-ykk@rock-chips.com> References: <1422975418-13302-1-git-send-email-ykk@rock-chips.com> Cc: Mark Rutland , alsa-devel@alsa-project.org, Heiko Stuebner , djkurtz@chromium.org, dianders@chromium.org, Yakir Yang , mmind00@googlemail.com, Pawel Moll , linux-rockchip@lists.infradead.org, Sean Cross , devicetree@vger.kernel.org, Arnd Bergmann , Ian Campbell , Jyri Sarha , Ben Zhang , Rob Herring , dri-devel@lists.freedesktop.org, marcheu@chromium.org, linux-arm-kernel@lists.infradead.org, Mark Yao , Fabio Estevam , linux-kernel@vger.kernel.org, Rob Clark , Daniel Vetter , Kumar Gala , Shawn Guo Subject: [alsa-devel] [PATCH v3 06/15] drm: bridge/dw_hdmi: adjust n/cts setting order X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP This patch changes the order to: - write CTS3 CTS_manual = 0 - write CTS3 N_shift = 0 - write CTS3 CTS value - write CTS2 CTS value - write CTS1 CTS value - write N3 N value - write N2 N value - write N1 N value Signed-off-by: Yakir Yang --- Changes in v3: - Only adjust the n/cts setting order Changes in v2: None drivers/gpu/drm/bridge/dw_hdmi.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c index 262163f..81309df 100644 --- a/drivers/gpu/drm/bridge/dw_hdmi.c +++ b/drivers/gpu/drm/bridge/dw_hdmi.c @@ -199,20 +199,20 @@ static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, static void hdmi_set_clock_regenerator(struct dw_hdmi *hdmi, unsigned int n, unsigned int cts) { - hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); - hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); - hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); + /* Must be set/cleared first */ + hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); /* nshift factor = 0 */ hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); - /* Must be set/cleared first */ - hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); - - hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); - hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); + hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); + hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); + + hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); + hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); + hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); } static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,