From patchwork Thu Feb 5 02:19:31 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yang.a.fang@intel.com X-Patchwork-Id: 5780761 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A97709F38E for ; Thu, 5 Feb 2015 02:20:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A7BFE20279 for ; Thu, 5 Feb 2015 02:20:14 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 8D24120222 for ; Thu, 5 Feb 2015 02:20:12 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 03DAB261736; Thu, 5 Feb 2015 03:20:10 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id D9F7C2606E1; Thu, 5 Feb 2015 03:20:04 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id C8544260712; Thu, 5 Feb 2015 03:20:00 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by alsa0.perex.cz (Postfix) with ESMTP id BFA152606E1 for ; Thu, 5 Feb 2015 03:19:53 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 04 Feb 2015 18:19:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,521,1418112000"; d="scan'208";a="673028902" Received: from mocha.sc.intel.com ([143.183.249.83]) by fmsmga002.fm.intel.com with ESMTP; 04 Feb 2015 18:19:51 -0800 From: yang.a.fang@intel.com To: broonie@kernel.org, lgirdwood@gmail.com Date: Wed, 4 Feb 2015 18:19:31 -0800 Message-Id: <1423102772-11426-1-git-send-email-yang.a.fang@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1422993828-29292-1-git-send-email-yang.a.fang@intel.com> References: <1422993828-29292-1-git-send-email-yang.a.fang@intel.com> Cc: alsa-devel@alsa-project.org, denny.iriawan@intel.com, harshapriya.n@intel.com, praveen.k.jain@intel.com, kevin.strasser@intel.com, vinod.koul@intel.com, "Fang, Yang A" , kevin.strasser@linux.intel.com, mengdong.lin@intel.com, bardliao@realtek.com Subject: [alsa-devel] [PATCH v4 1/2] ASoC: rt5645: add API to select ASRC clock source X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: "Fang, Yang A" This patch defines an API to select the clock source for specified filters. Signed-off-by: Fang, Yang A Acked-by: Kevin Strasser --- sound/soc/codecs/rt5645.c | 81 +++++++++++++++++++++++++++++++++++++++++++++ sound/soc/codecs/rt5645.h | 72 +++++++++++++++++----------------------- 2 files changed, 112 insertions(+), 41 deletions(-) diff --git a/sound/soc/codecs/rt5645.c b/sound/soc/codecs/rt5645.c index 21b2d72..debf16c 100644 --- a/sound/soc/codecs/rt5645.c +++ b/sound/soc/codecs/rt5645.c @@ -613,6 +613,87 @@ static int is_using_asrc(struct snd_soc_dapm_widget *source, } +/** + * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters + * @codec: SoC audio codec device. + * @filter_mask: mask of filters. + * @clk_src: clock source + * + * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can + * only support standard 32fs or 64fs i2s format, ASRC should be enabled to + * support special i2s clock format such as Intel's 100fs(100 * sampling rate). + * ASRC function will track i2s clock and generate a corresponding system clock + * for codec. This function provides an API to select the clock source for a + * set of filters specified by the mask. And the codec driver will turn on ASRC + * for these filters if ASRC is selected as their clock source. + */ +int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec, + unsigned int filter_mask, unsigned int clk_src) +{ + unsigned int asrc2_mask = 0; + unsigned int asrc2_value = 0; + unsigned int asrc3_mask = 0; + unsigned int asrc3_value = 0; + + switch (clk_src) { + case RT5645_CLK_SEL_SYS: + case RT5645_CLK_SEL_I2S1_ASRC: + case RT5645_CLK_SEL_I2S2_ASRC: + case RT5645_CLK_SEL_SYS2: + break; + + default: + return -EINVAL; + } + + if (filter_mask & RT5645_DA_STEREO_FILTER) { + asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK; + asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK) + | (clk_src << RT5645_DA_STO_CLK_SEL_SFT); + } + + if (filter_mask & RT5645_DA_MONO_L_FILTER) { + asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK; + asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK) + | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT); + } + + if (filter_mask & RT5645_DA_MONO_R_FILTER) { + asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK; + asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK) + | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT); + } + + if (filter_mask & RT5645_AD_STEREO_FILTER) { + asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK; + asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK) + | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT); + } + + if (filter_mask & RT5645_AD_MONO_L_FILTER) { + asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK; + asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK) + | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT); + } + + if (filter_mask & RT5645_AD_MONO_R_FILTER) { + asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK; + asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK) + | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT); + } + + if (asrc2_mask) + snd_soc_update_bits(codec, RT5645_ASRC_2, + asrc2_mask, asrc2_value); + + if (asrc3_mask) + snd_soc_update_bits(codec, RT5645_ASRC_3, + asrc3_mask, asrc3_value); + + return 0; +} +EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src); + /* Digital Mixer */ static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = { SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, diff --git a/sound/soc/codecs/rt5645.h b/sound/soc/codecs/rt5645.h index 7454231..dbfd98c 100644 --- a/sound/soc/codecs/rt5645.h +++ b/sound/soc/codecs/rt5645.h @@ -1120,50 +1120,27 @@ #define RT5645_DMIC_2_M_NOR (0x0 << 8) #define RT5645_DMIC_2_M_ASYN (0x1 << 8) +/* ASRC clock source selection (0x84, 0x85) */ +#define RT5645_CLK_SEL_SYS (0x0) +#define RT5645_CLK_SEL_I2S1_ASRC (0x1) +#define RT5645_CLK_SEL_I2S2_ASRC (0x2) +#define RT5645_CLK_SEL_SYS2 (0x5) + /* ASRC Control 2 (0x84) */ -#define RT5645_MDA_L_M_MASK (0x1 << 15) -#define RT5645_MDA_L_M_SFT 15 -#define RT5645_MDA_L_M_NOR (0x0 << 15) -#define RT5645_MDA_L_M_ASYN (0x1 << 15) -#define RT5645_MDA_R_M_MASK (0x1 << 14) -#define RT5645_MDA_R_M_SFT 14 -#define RT5645_MDA_R_M_NOR (0x0 << 14) -#define RT5645_MDA_R_M_ASYN (0x1 << 14) -#define RT5645_MAD_L_M_MASK (0x1 << 13) -#define RT5645_MAD_L_M_SFT 13 -#define RT5645_MAD_L_M_NOR (0x0 << 13) -#define RT5645_MAD_L_M_ASYN (0x1 << 13) -#define RT5645_MAD_R_M_MASK (0x1 << 12) -#define RT5645_MAD_R_M_SFT 12 -#define RT5645_MAD_R_M_NOR (0x0 << 12) -#define RT5645_MAD_R_M_ASYN (0x1 << 12) -#define RT5645_ADC_M_MASK (0x1 << 11) -#define RT5645_ADC_M_SFT 11 -#define RT5645_ADC_M_NOR (0x0 << 11) -#define RT5645_ADC_M_ASYN (0x1 << 11) -#define RT5645_STO_DAC_M_MASK (0x1 << 5) -#define RT5645_STO_DAC_M_SFT 5 -#define RT5645_STO_DAC_M_NOR (0x0 << 5) -#define RT5645_STO_DAC_M_ASYN (0x1 << 5) -#define RT5645_I2S1_R_D_MASK (0x1 << 4) -#define RT5645_I2S1_R_D_SFT 4 -#define RT5645_I2S1_R_D_DIS (0x0 << 4) -#define RT5645_I2S1_R_D_EN (0x1 << 4) -#define RT5645_I2S2_R_D_MASK (0x1 << 3) -#define RT5645_I2S2_R_D_SFT 3 -#define RT5645_I2S2_R_D_DIS (0x0 << 3) -#define RT5645_I2S2_R_D_EN (0x1 << 3) -#define RT5645_PRE_SCLK_MASK (0x3) -#define RT5645_PRE_SCLK_SFT 0 -#define RT5645_PRE_SCLK_512 (0x0) -#define RT5645_PRE_SCLK_1024 (0x1) -#define RT5645_PRE_SCLK_2048 (0x2) +#define RT5645_DA_STO_CLK_SEL_MASK (0xf << 12) +#define RT5645_DA_STO_CLK_SEL_SFT 12 +#define RT5645_DA_MONOL_CLK_SEL_MASK (0xf << 8) +#define RT5645_DA_MONOL_CLK_SEL_SFT 8 +#define RT5645_DA_MONOR_CLK_SEL_MASK (0xf << 4) +#define RT5645_DA_MONOR_CLK_SEL_SFT 4 +#define RT5645_AD_STO1_CLK_SEL_MASK (0xf << 0) +#define RT5645_AD_STO1_CLK_SEL_SFT 0 /* ASRC Control 3 (0x85) */ -#define RT5645_I2S1_RATE_MASK (0xf << 12) -#define RT5645_I2S1_RATE_SFT 12 -#define RT5645_I2S2_RATE_MASK (0xf << 8) -#define RT5645_I2S2_RATE_SFT 8 +#define RT5645_AD_MONOL_CLK_SEL_MASK (0xf << 4) +#define RT5645_AD_MONOL_CLK_SEL_SFT 4 +#define RT5645_AD_MONOR_CLK_SEL_MASK (0xf << 0) +#define RT5645_AD_MONOR_CLK_SEL_SFT 0 /* ASRC Control 4 (0x89) */ #define RT5645_I2S1_PD_MASK (0x7 << 12) @@ -2189,6 +2166,19 @@ enum { CODEC_TYPE_RT5650, }; +/* filter mask */ +enum { + RT5645_DA_STEREO_FILTER = 0x1, + RT5645_DA_MONO_L_FILTER = (0x1 << 1), + RT5645_DA_MONO_R_FILTER = (0x1 << 2), + RT5645_AD_STEREO_FILTER = (0x1 << 3), + RT5645_AD_MONO_L_FILTER = (0x1 << 4), + RT5645_AD_MONO_R_FILTER = (0x1 << 5), +}; + +int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec, + unsigned int filter_mask, unsigned int clk_src); + struct rt5645_priv { struct snd_soc_codec *codec; struct rt5645_platform_data pdata;