| Message ID | 1423993031-29474-1-git-send-email-nicoleotsuka@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 6c8ca30eec7b6f8eb09c957e8dcced89e5f100c7 |
| Headers | show |
On Sun, Feb 15, 2015 at 01:37:11AM -0800, Nicolin Chen wrote: > According to i.MX6 Series Reference Manual, the formula to calculate > the sys clock is This doesn't apply against current code, pleae check and resend.
On Tue, Feb 24, 2015 at 05:26:42PM +0900, Mark Brown wrote: > On Sun, Feb 15, 2015 at 01:37:11AM -0800, Nicolin Chen wrote: > > According to i.MX6 Series Reference Manual, the formula to calculate > > the sys clock is > > This doesn't apply against current code, pleae check and resend. That's strange...I downloaded it from Patchwork and tried to apply it on the latest for-next. It doesn't give me any error... And I git-formated a new one but it doesn't look so different from the one in the maillist... Thank you Nicolin
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index d7365c5..3e7c644 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -603,7 +603,7 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, factor = (div2 + 1) * (7 * psr + 1) * 2; for (i = 0; i < 255; i++) { - tmprate = freq * factor * (i + 2); + tmprate = freq * factor * (i + 1); if (baudclk_is_used) clkrate = clk_get_rate(ssi_private->baudclk);
According to i.MX6 Series Reference Manual, the formula to calculate the sys clock is sysclk rate = bclk rate * (div2 + 1) * (7 * psr + 1) * (pm + 1) * 2 Commit aafa85e71a75 ("ASoC: fsl_ssi: Add DAI master mode support for SSI on i.MX series") added the divisor calculation which relies on the clk_round_rate(). However, at that time, clk_round_rate() didn't provide closest clock rates for some cases because it might not use a correct rounding policy. So using the original formula (pm + 1) for PM divisor was not able to give us a desired clock rate. And then we used (pm + 2) to do the trick. However, the clk-divider driver has been refined a lot since commit b11d282dbea2 ("clk: divider: fix rate calculation for fractional rates") Now using (pm + 2) trick would result an incorrect clock rate. So this patch fixes the problem by removing the useless trick. Reported-by: Stephane Cerveau <scerveau@voxtok.com> Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> --- [ I also checked that only 3.18 stable tree has the refinements for clk-divider driver, so I guess it might not be able to apply to previous long-term trees if being treated as bug fix. -- Nicolin ] sound/soc/fsl/fsl_ssi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)