Message ID | 1424538689-6330-1-git-send-email-niederp@physik.uni-kl.de (mailing list archive) |
---|---|
State | Accepted |
Commit | 8af4baa7087a0ae74c6ee29d4d979a60e14b119e |
Headers | show |
On Sat, Feb 21, 2015 at 06:11:29PM +0100, Thomas Niederprüm wrote: > This patch fixes faulty behaviour in a setup where the input clock for the > SRG is fed through the CLKR/CLKX pin but the McBSP is configured to be > master (SND_SOC_DAIFMT_CBS_CFS). In that case of course CLKR/CLKX must > not be configured as output pin. Otherwise the input clock is messed up > horribly. Applied, but please as covered in SubmittingPatches word wrap your changelog entries to less than 80 columns - this is especially important for the subject line. Please also remember to CC maintainers on patches, the reason you've had to resend this patch is that you didn't originally send it to me (which means the RESEND tag both makes the subject line even longer and makes me a bit grumpy).
diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c index bd3ef2a..662269c 100644 --- a/sound/soc/omap/omap-mcbsp.c +++ b/sound/soc/omap/omap-mcbsp.c @@ -530,8 +530,19 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, case OMAP_MCBSP_SYSCLK_CLKX_EXT: regs->srgr2 |= CLKSM; + regs->pcr0 |= SCLKME; + /* + * If McBSP is master but yet the CLKX/CLKR pin drives the SRG, + * disable output on those pins. This enables to inject the + * reference clock through CLKX/CLKR. For this to work + * set_dai_sysclk() _needs_ to be called after set_dai_fmt(). + */ + regs->pcr0 &= ~CLKXM; + break; case OMAP_MCBSP_SYSCLK_CLKR_EXT: regs->pcr0 |= SCLKME; + /* Disable ouput on CLKR pin in master mode */ + regs->pcr0 &= ~CLKRM; break; default: err = -ENODEV;