From patchwork Tue May 5 22:14:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Cernekee X-Patchwork-Id: 6344541 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 56ADC9F32E for ; Tue, 5 May 2015 22:16:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 703E520251 for ; Tue, 5 May 2015 22:16:08 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 3899220221 for ; Tue, 5 May 2015 22:16:07 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 6315C2657E5; Wed, 6 May 2015 00:16:06 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id B6E8526149E; Wed, 6 May 2015 00:14:38 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 115B12619F7; Wed, 6 May 2015 00:14:37 +0200 (CEST) Received: from mail-ie0-f182.google.com (mail-ie0-f182.google.com [209.85.223.182]) by alsa0.perex.cz (Postfix) with ESMTP id BBEB62604C6 for ; Wed, 6 May 2015 00:14:26 +0200 (CEST) Received: by iecnq11 with SMTP id nq11so880275iec.3 for ; Tue, 05 May 2015 15:14:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=82XNQ2ewJZRKCd9CBVk9niEwVrSobEKAug+U+SdvY9c=; b=WllML3gmcL4TlhBkcoypFTxniavZeFbXsKN25QZNhwTTXv/7Pe3wswRm9EbMdPLiQp 6ze1aqe4417TtgaRv2ms9P4qzc2ZBsUwRJZGLn71gDX3bOwUzHGFJTQI+xq+HcKsRMmy wwy4OWbArPmPtRAng2Yw2hIVLtFHMXQHLB61gkNsZoa2BrsP6mJQakO0MnRJkgx16Oc+ OnalbB6Y7SA9lQyG8dF8Q3GP4mjLDVUocwPWTOMrJMhHvZuOKzNr07V13LhsW/pDFrv+ L6f/kZI9/js+x1XrjG5XfwZEqtdr8RbefZrovcZAqZMD6bEcRpK8cSeuvvoFB9gpi5U4 LdqA== X-Gm-Message-State: ALoCoQlpxWgJbB9cz31EFemX7m4g0IxQSG8nZf2wUXD55L9irZxeJJYvf8cVhHLjMvsuLMm+jAB/ X-Received: by 10.107.135.35 with SMTP id j35mr36078937iod.91.1430864066102; Tue, 05 May 2015 15:14:26 -0700 (PDT) Received: from kcl.mtv.corp.google.com ([172.22.66.15]) by mx.google.com with ESMTPSA id 9sm12629669iom.29.2015.05.05.15.14.23 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 05 May 2015 15:14:24 -0700 (PDT) From: Kevin Cernekee To: lgirdwood@gmail.com, broonie@kernel.org Date: Tue, 5 May 2015 15:14:14 -0700 Message-Id: <1430864057-3848-3-git-send-email-cernekee@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c In-Reply-To: <1430864057-3848-1-git-send-email-cernekee@chromium.org> References: <1430864057-3848-1-git-send-email-cernekee@chromium.org> Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, lars@metafoo.de, abrestic@chromium.org, linux-kernel@vger.kernel.org, dgreid@chromium.org, olofj@chromium.org Subject: [alsa-devel] [PATCH V4 2/5] regmap: Use regcache_mark_dirty() to indicate power loss or reset X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP Existing regmap users call regcache_mark_dirty() as part of the suspend/resume sequence, to tell regcache that non-default values need to be resynced post-resume. Add an internal "no_sync_defaults" regmap flag to remember this state, so that regcache_sync() can differentiate between these two cases: 1) HW was reset, so any cache values that match map->reg_defaults can be safely skipped. On some chips there are a lot of registers in the reg_defaults list, so this optimization speeds things up quite a bit. 2) HW was not reset (maybe it was just clock-gated), so if we cached any writes, they should be sent to the hardware regardless of whether they match the HW default. Currently this will write out all values in the regcache, since we don't maintain per-register dirty bits. Suggested-by: Mark Brown Signed-off-by: Kevin Cernekee --- drivers/base/regmap/internal.h | 3 +++ drivers/base/regmap/regcache.c | 19 +++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/base/regmap/internal.h b/drivers/base/regmap/internal.h index a13587b5c2be..b2b2849fc6d3 100644 --- a/drivers/base/regmap/internal.h +++ b/drivers/base/regmap/internal.h @@ -131,7 +131,10 @@ struct regmap { struct reg_default *reg_defaults; const void *reg_defaults_raw; void *cache; + /* if set, the cache contains newer data than the HW */ u32 cache_dirty; + /* if set, the HW registers are known to match map->reg_defaults */ + bool no_sync_defaults; struct reg_default *patch; int patch_regs; diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c index c58493eaf050..b9862d741a56 100644 --- a/drivers/base/regmap/regcache.c +++ b/drivers/base/regmap/regcache.c @@ -254,6 +254,10 @@ static bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg, { int ret; + /* If we don't know the chip just got reset, then sync everything. */ + if (!map->no_sync_defaults) + return true; + /* Is this the hardware default? If so skip. */ ret = regcache_lookup_reg(map, reg); if (ret >= 0 && val == map->reg_defaults[ret].def) @@ -352,6 +356,7 @@ out: /* Restore the bypass state */ map->async = false; map->cache_bypass = bypass; + map->no_sync_defaults = false; map->unlock(map->lock_arg); regmap_async_complete(map); @@ -407,6 +412,7 @@ out: /* Restore the bypass state */ map->cache_bypass = bypass; map->async = false; + map->no_sync_defaults = false; map->unlock(map->lock_arg); regmap_async_complete(map); @@ -471,18 +477,23 @@ void regcache_cache_only(struct regmap *map, bool enable) EXPORT_SYMBOL_GPL(regcache_cache_only); /** - * regcache_mark_dirty: Mark the register cache as dirty + * regcache_mark_dirty: Indicate that HW registers were reset to default values * * @map: map to mark * - * Mark the register cache as dirty, for example due to the device - * having been powered down for suspend. If the cache is not marked - * as dirty then the cache sync will be suppressed. + * Inform regcache that the device has been powered down or reset, so that + * on resume, regcache_sync() knows to write out all non-default values + * stored in the cache. + * + * If this function is not called, regcache_sync() will assume that + * the hardware state still matches the cache state, modulo any writes that + * happened when cache_only was true. */ void regcache_mark_dirty(struct regmap *map) { map->lock(map->lock_arg); map->cache_dirty = true; + map->no_sync_defaults = true; map->unlock(map->lock_arg); } EXPORT_SYMBOL_GPL(regcache_mark_dirty);