From patchwork Thu Jul 9 03:32:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Koro Chen X-Patchwork-Id: 6752881 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C76EDC05AC for ; Thu, 9 Jul 2015 03:33:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 09C222064C for ; Thu, 9 Jul 2015 03:33:13 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 9642E205B5 for ; Thu, 9 Jul 2015 03:33:11 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 35263265B6C; Thu, 9 Jul 2015 05:33:10 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id 5849F265B90; Thu, 9 Jul 2015 05:33:01 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 6586B265C97; Thu, 9 Jul 2015 05:33:00 +0200 (CEST) Received: from mailgw01.mediatek.com (unknown [210.61.82.183]) by alsa0.perex.cz (Postfix) with ESMTP id A0D54265B6C for ; Thu, 9 Jul 2015 05:32:54 +0200 (CEST) X-Listener-Flag: 11101 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1035658903; Thu, 09 Jul 2015 11:32:52 +0800 Received: from mtkslt301 (10.21.14.114) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Thu, 9 Jul 2015 11:32:50 +0800 Received: by mtkslt301 (Postfix, from userid 11333) id CAB15183AC2; Thu, 9 Jul 2015 11:32:50 +0800 (CST) From: Koro Chen To: Date: Thu, 9 Jul 2015 11:32:05 +0800 Message-ID: <1436412725-55129-1-git-send-email-koro.chen@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty MIME-Version: 1.0 X-MTK: N Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, srv_heupstream@mediatek.com, s.hauer@pengutronix.de, linux-kernel@vger.kernel.org, djkurtz@chromium.org, Koro Chen , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH v2] arm64: dts: mt8173: Add afe device node X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP This adds afe (audio front end) device node to the MT8173 dtsi file. Signed-off-by: Koro Chen Reviewed-by: Daniel Kurtz --- This patch is based on Matthias's tree: https://github.com/mbgg/linux-mediatek branch: v4.2-next/arm64 Changes since v1: - change node name to afe: audio-controller@11220000 --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 0696f8f..ce9255a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include "mt8173-pinfunc.h" @@ -393,6 +394,37 @@ #size-cells = <0>; status = "disabled"; }; + + afe: audio-controller@11220000 { + compatible = "mediatek,mt8173-afe-pcm"; + reg = <0 0x11220000 0 0x1000>; + interrupts = ; + power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; + clocks = <&infracfg CLK_INFRA_AUDIO>, + <&topckgen CLK_TOP_AUDIO_SEL>, + <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&topckgen CLK_TOP_APLL1_DIV0>, + <&topckgen CLK_TOP_APLL2_DIV0>, + <&topckgen CLK_TOP_I2S0_M_SEL>, + <&topckgen CLK_TOP_I2S1_M_SEL>, + <&topckgen CLK_TOP_I2S2_M_SEL>, + <&topckgen CLK_TOP_I2S3_M_SEL>, + <&topckgen CLK_TOP_I2S3_B_SEL>; + clock-names = "infra_sys_audio_clk", + "top_pdn_audio", + "top_pdn_aud_intbus", + "bck0", + "bck1", + "i2s0_m", + "i2s1_m", + "i2s2_m", + "i2s3_m", + "i2s3_b"; + assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, + <&topckgen CLK_TOP_AUD_2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, + <&topckgen CLK_TOP_APLL2>; + }; }; };