From patchwork Tue Nov 3 01:33:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 7539251 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2D91B9F399 for ; Tue, 3 Nov 2015 01:37:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3C33C2062F for ; Tue, 3 Nov 2015 01:37:03 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 1578B20306 for ; Tue, 3 Nov 2015 01:37:02 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 41BB8265232; Tue, 3 Nov 2015 02:37:01 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,NO_DNS_FOR_FROM, RCVD_IN_DNSWL_LOW, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 3447D265043; Tue, 3 Nov 2015 02:35:15 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id F13CC265043; Tue, 3 Nov 2015 02:35:13 +0100 (CET) Received: from mail-pa0-f54.google.com (mail-pa0-f54.google.com [209.85.220.54]) by alsa0.perex.cz (Postfix) with ESMTP id 0F3E52650B0 for ; Tue, 3 Nov 2015 02:34:53 +0100 (CET) Received: by pacfv9 with SMTP id fv9so2731674pac.3 for ; Mon, 02 Nov 2015 17:34:52 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rRs7XckOeRkMrq4Av/mlOq/pti8CvvBBGPOHHZWe7fE=; b=cFRQm8UCjEecy6oNXqn1AA4rXWZUyHASoR7YsjAwNwAoObGdMhTy9fx2s2kK+AG54A ZLlDCvnVRJGYJnONazGwD3YhQ0d5ULT8wNBiBXSw0GqefOm61Rbv75pCms95SV4VcguA zWOx8Vs8QC2m8jVgmifVIjvL1WcnmR6/hOszUmvEjTMSuFeYBF1zmWPO0iKqZNAfqPh/ hlM5NMX/AF8VVY/njBW8CnQS7B5tUIqBSxFies9M8eKtUhCFF81SWS2dQHPKZCmYeNR8 Wz/9b1ZS6H0GiDJYZ9jMYvvfx5Lxd7mSpyJ6wthrZVTW27z/Vqvw7yLY+g0jtWbybNhO 7xHw== X-Received: by 10.68.136.10 with SMTP id pw10mr30544465pbb.89.1446514492015; Mon, 02 Nov 2015 17:34:52 -0800 (PST) Received: from localhost.localdomain ([103.47.144.138]) by smtp.gmail.com with ESMTPSA id yp5sm26371345pac.38.2015.11.02.17.34.43 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 02 Nov 2015 17:34:51 -0800 (PST) From: Caesar Wang To: Heiko Stuebner , Mark Brown Date: Tue, 3 Nov 2015 09:33:57 +0800 Message-Id: <1446514438-13922-5-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1446514438-13922-1-git-send-email-wxt@rock-chips.com> References: <1446514438-13922-1-git-send-email-wxt@rock-chips.com> Cc: alsa-devel@alsa-project.org, Liam Girdwood , linux-kernel@vger.kernel.org, Takashi Iwai , Doug Anderson , linux-rockchip@lists.infradead.org, Dylan Reid , Cheng-Yi Chiang , Sonny Rao , linux-arm-kernel@lists.infradead.org, Caesar Wang Subject: [alsa-devel] [PATCH v1 4/5] ASoC: rockchip-max98090: Add the divider clock for cpu X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP Add to set the cpu/codec DAI configure, let's divider the Transmit/Receive clocks for cpu. In master mode, The SCLK and LRCK are configured as output, this patch should can set each divider to arrange the clock distribution. Signed-off-by: Caesar Wang --- Changes in v1: None sound/soc/rockchip/rockchip_max98090.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/sound/soc/rockchip/rockchip_max98090.c b/sound/soc/rockchip/rockchip_max98090.c index a6ff221..e1cdd40 100644 --- a/sound/soc/rockchip/rockchip_max98090.c +++ b/sound/soc/rockchip/rockchip_max98090.c @@ -75,8 +75,25 @@ static int rk_aif1_hw_params(struct snd_pcm_substream *substream, struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; struct snd_soc_dai *codec_dai = rtd->codec_dai; + int dai_fmt = rtd->card->dai_link->dai_fmt; int mclk; + /* set codec DAI configuration */ + ret = snd_soc_dai_set_fmt(codec_dai, dai_fmt); + if (ret < 0) { + dev_err(codec_dai->dev, + "failed to set the format for codec side\n"); + return ret; + } + + /* set cpu DAI configuration */ + ret = snd_soc_dai_set_fmt(cpu_dai, dai_fmt); + if (ret < 0) { + dev_err(codec_dai->dev, + "failed to set the format for cpu side\n"); + return ret; + } + switch (params_rate(params)) { case 8000: case 16000: @@ -110,6 +127,21 @@ static int rk_aif1_hw_params(struct snd_pcm_substream *substream, return ret; } + /* The codec is master mode, that's not needed set clkdiv for cpu */ + if ((dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM) + return ret; + + /* the LRCK clock for cpu */ + ret = snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_BCLK, + (mclk / 4) / params_rate(params)); + if (ret < 0) + return ret; + + /* the SCLK clock for cpu */ + snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_MCLK, 4); + if (ret < 0) + return ret; + return ret; }