From patchwork Fri Nov 6 11:38:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 7568511 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3BA479F71A for ; Fri, 6 Nov 2015 11:39:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5E08D2073B for ; Fri, 6 Nov 2015 11:39:51 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 3C99D20732 for ; Fri, 6 Nov 2015 11:39:50 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 56E0D2604F0; Fri, 6 Nov 2015 12:39:49 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,NO_DNS_FOR_FROM, RCVD_IN_DNSWL_LOW, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 958A2260535; Fri, 6 Nov 2015 12:39:20 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id C8185260535; Fri, 6 Nov 2015 12:39:19 +0100 (CET) Received: from mail-pa0-f65.google.com (mail-pa0-f65.google.com [209.85.220.65]) by alsa0.perex.cz (Postfix) with ESMTP id 1B47B260421 for ; Fri, 6 Nov 2015 12:38:51 +0100 (CET) Received: by padda3 with SMTP id da3so14810558pad.1 for ; Fri, 06 Nov 2015 03:38:50 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=T1zBdbdrwXGsb1XfJGqSUdNaxuxikJemQVg7mlLeMrw=; b=HcM9aYYeAIHZMncsxMsSp8t0eqx7VIfer+HLMwm74esOEIfYpZu5ECuEhdGDDhArGW Vln24cxTjT6y36GYvfoUQDNNwvw0+BWNlc2wUh8qCXB+zzJUUxbnFov0PKKRjbzT6DYq xricgcjd+oyQYDRo5G4S67AyhsIBUY1MW4Lem9yBOUcNCml1RmuVjJ4hq6ccsyjZeYu1 V5+awavO6Ai7R+LgmkiJ1YSaluBd+WFhKEWgAUSq/AYd8eG1OsL4Z7qGgsKSmZXkKfln TPfsjYNMvJlT0CxDppdU/V3yA7lfIxCr6mib18bM8FMac8+VNrHtZDBBrAy8dMuMwCj8 MlbQ== X-Received: by 10.66.228.199 with SMTP id sk7mr17104781pac.78.1446809929909; Fri, 06 Nov 2015 03:38:49 -0800 (PST) Received: from localhost.localdomain ([103.46.142.42]) by smtp.gmail.com with ESMTPSA id pn8sm13672592pbb.16.2015.11.06.03.38.39 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 06 Nov 2015 03:38:48 -0800 (PST) From: Caesar Wang To: Heiko Stuebner , Mark Brown Date: Fri, 6 Nov 2015 19:38:14 +0800 Message-Id: <1446809896-11254-2-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1446809896-11254-1-git-send-email-wxt@rock-chips.com> References: <1446809896-11254-1-git-send-email-wxt@rock-chips.com> Cc: kmixter@chromium.org, alsa-devel@alsa-project.org, Liam Girdwood , linux-kernel@vger.kernel.org, Takashi Iwai , Doug Anderson , linux-rockchip@lists.infradead.org, Dylan Reid , Caesar Wang , Sonny Rao , benchan@chromium.org, linux-arm-kernel@lists.infradead.org, Cheng-Yi Chiang Subject: [alsa-devel] [PATCH v2 1/3] ASoC: rockchip: i2s: change bclk and lrck according to sample rates X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP This patch sets the dividers autonomously. when i2s works on master mode, and sample rates changed. We need to change bclk and lrck at the same time for cpu internal side. As the input source clock to the module is MCLK_I2S, and by the divider of the module, the clock generator generates SCLK and LRCK to transmitter and receiver. Signed-off-by: Caesar Wang --- Changes in v2: - move the set clock divider into rockchip i2s. sound/soc/rockchip/rockchip_i2s.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index b936102..b349935 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -41,6 +41,7 @@ struct rk_i2s_dev { */ bool tx_start; bool rx_start; + bool is_master_mode; }; static int i2s_runtime_suspend(struct device *dev) @@ -174,9 +175,11 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, case SND_SOC_DAIFMT_CBS_CFS: /* Set source clock in Master mode */ val = I2S_CKR_MSS_MASTER; + i2s->is_master_mode = true; break; case SND_SOC_DAIFMT_CBM_CFM: val = I2S_CKR_MSS_SLAVE; + i2s->is_master_mode = false; break; default: return -EINVAL; @@ -227,6 +230,26 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, { struct rk_i2s_dev *i2s = to_info(dai); unsigned int val = 0; + unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck; + + if (i2s->is_master_mode) { + mclk_rate = clk_get_rate(i2s->mclk); + bclk_rate = 2 * 32 * params_rate(params); + if (bclk_rate && mclk_rate % bclk_rate) + return -EINVAL; + + div_bclk = mclk_rate / bclk_rate; + div_lrck = bclk_rate / params_rate(params); + regmap_update_bits(i2s->regmap, I2S_CKR, + I2S_CKR_MDIV_MASK, + I2S_CKR_MDIV(div_bclk)); + + regmap_update_bits(i2s->regmap, I2S_CKR, + I2S_CKR_TSD_MASK | + I2S_CKR_RSD_MASK, + I2S_CKR_TSD(div_lrck) | + I2S_CKR_RSD(div_lrck)); + } switch (params_format(params)) { case SNDRV_PCM_FORMAT_S8: