From patchwork Wed Dec 9 10:32:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Keeping X-Patchwork-Id: 7807211 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0D0029FC62 for ; Wed, 9 Dec 2015 10:33:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3095D20483 for ; Wed, 9 Dec 2015 10:33:23 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id BE797204AF for ; Wed, 9 Dec 2015 10:33:21 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 7C16826044B; Wed, 9 Dec 2015 11:33:15 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, NO_DNS_FOR_FROM,RCVD_IN_DNSWL_LOW,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 315F8260417; Wed, 9 Dec 2015 11:33:12 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id C1308260418; Wed, 9 Dec 2015 11:33:10 +0100 (CET) Received: from metanate.com (dougal.metanate.com [90.155.101.14]) by alsa0.perex.cz (Postfix) with ESMTP id 22352260412 for ; Wed, 9 Dec 2015 11:33:05 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=simple/simple; d=metanate.com; s=stronger; h=Message-Id:Date:Subject:Cc:To:From; bh=J/XCajx4waIIlwgl9jtRCA0ngplF4JgbUyAQWTRJ+ww=; b=uKXnKwKXSBew4e7ivU6gdcg5jZsYcvz9Tyt9S3h8CBwxCwggP3sGnTBk5x+dkWUwQhgUue6lTVIcuAtO9ZI32WyWyWzw29QgNpk2kUkGaebKfNqSqUNDmubXUwTnI1odW0nGYSW2s5VOg0+OXlhygTiIbV+J5yHNXNCw9EPkkCHT7FuUahPQZxHM2LtrwaJaOsM+yReghf2/77EigZVsNEJ8C3wwyaHlektB1mknChKwYpYs7RhdedSzGWdqtzGROqY5ItY1PtGtlY2XfrO6ieNnbNyyxZi195x60+xs9+Rb8zeeH+1ihdg0KELBFBxsw2ibYtl+KnEJyhm13i1YVw==; Received: from brian ([192.168.88.1] helo=leela.metanate.com) by shrek.metanate.com with esmtpsa (TLSv1.2:AES128-SHA256:128) (Exim 4.83_RC2) (envelope-from ) id 1a6c38-0000PN-G4; Wed, 09 Dec 2015 10:32:42 +0000 From: John Keeping To: linux-rockchip@lists.infradead.org Date: Wed, 9 Dec 2015 10:32:26 +0000 Message-Id: <1449657147-26959-1-git-send-email-john@metanate.com> X-Mailer: git-send-email 2.6.3.462.gbe2c914 Cc: alsa-devel@alsa-project.org, Heiko Stuebner , linux-kernel@vger.kernel.org, Takashi Iwai , Liam Girdwood , Mark Brown , John Keeping , linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH 1/2] ASoC: rockchip: i2s: separate capture and playback X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP If we only clear the tx/rx state when both are disabled it is not possible to start/stop one multiple times while the other is running. Since the two are independently controlled, treat them as such and remove the false dependency between capture and playback. Signed-off-by: John Keeping --- sound/soc/rockchip/rockchip_i2s.c | 72 +++++++++++++++++---------------------- 1 file changed, 32 insertions(+), 40 deletions(-) diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index 83b1b9c..acc6225 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -82,8 +82,8 @@ static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE); regmap_update_bits(i2s->regmap, I2S_XFER, - I2S_XFER_TXS_START | I2S_XFER_RXS_START, - I2S_XFER_TXS_START | I2S_XFER_RXS_START); + I2S_XFER_TXS_START, + I2S_XFER_TXS_START); i2s->tx_start = true; } else { @@ -92,27 +92,23 @@ static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE); - if (!i2s->rx_start) { - regmap_update_bits(i2s->regmap, I2S_XFER, - I2S_XFER_TXS_START | - I2S_XFER_RXS_START, - I2S_XFER_TXS_STOP | - I2S_XFER_RXS_STOP); + regmap_update_bits(i2s->regmap, I2S_XFER, + I2S_XFER_TXS_START, + I2S_XFER_TXS_STOP); - regmap_update_bits(i2s->regmap, I2S_CLR, - I2S_CLR_TXC | I2S_CLR_RXC, - I2S_CLR_TXC | I2S_CLR_RXC); + regmap_update_bits(i2s->regmap, I2S_CLR, + I2S_CLR_TXC, + I2S_CLR_TXC); - regmap_read(i2s->regmap, I2S_CLR, &val); + regmap_read(i2s->regmap, I2S_CLR, &val); - /* Should wait for clear operation to finish */ - while (val) { - regmap_read(i2s->regmap, I2S_CLR, &val); - retry--; - if (!retry) { - dev_warn(i2s->dev, "fail to clear\n"); - break; - } + /* Should wait for clear operation to finish */ + while (val & I2S_CLR_TXC) { + regmap_read(i2s->regmap, I2S_CLR, &val); + retry--; + if (!retry) { + dev_warn(i2s->dev, "fail to clear\n"); + break; } } } @@ -128,8 +124,8 @@ static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE); regmap_update_bits(i2s->regmap, I2S_XFER, - I2S_XFER_TXS_START | I2S_XFER_RXS_START, - I2S_XFER_TXS_START | I2S_XFER_RXS_START); + I2S_XFER_RXS_START, + I2S_XFER_RXS_START); i2s->rx_start = true; } else { @@ -138,27 +134,23 @@ static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE); - if (!i2s->tx_start) { - regmap_update_bits(i2s->regmap, I2S_XFER, - I2S_XFER_TXS_START | - I2S_XFER_RXS_START, - I2S_XFER_TXS_STOP | - I2S_XFER_RXS_STOP); + regmap_update_bits(i2s->regmap, I2S_XFER, + I2S_XFER_RXS_START, + I2S_XFER_RXS_STOP); - regmap_update_bits(i2s->regmap, I2S_CLR, - I2S_CLR_TXC | I2S_CLR_RXC, - I2S_CLR_TXC | I2S_CLR_RXC); + regmap_update_bits(i2s->regmap, I2S_CLR, + I2S_CLR_RXC, + I2S_CLR_RXC); - regmap_read(i2s->regmap, I2S_CLR, &val); + regmap_read(i2s->regmap, I2S_CLR, &val); - /* Should wait for clear operation to finish */ - while (val) { - regmap_read(i2s->regmap, I2S_CLR, &val); - retry--; - if (!retry) { - dev_warn(i2s->dev, "fail to clear\n"); - break; - } + /* Should wait for clear operation to finish */ + while (val & I2S_CLR_RXC) { + regmap_read(i2s->regmap, I2S_CLR, &val); + retry--; + if (!retry) { + dev_warn(i2s->dev, "fail to clear\n"); + break; } } }