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BN3PR0301MB1251; 5:yLgwFP+atIVNey63lzsoQ557AobqeMGZN007Zykypa5gjue3bZ5IwjSFmq3BGmpbiIT8pkQviI+rmEh4VW7YClRFq3ilYvOU6j30pMgkL/i09f+e/FxI1UL3UC1ALpoU0w4MDk3N8zFV3an/ohCJXg==; 24:HN6lsptA3rLI+tX/XS70qTTBuZtHo1LDkgm69mAFdSARJSRxDFpdGgPRiAXaG4s9ShPx5Iaxh2uME3aoIjUo+2HBq90dF0u0JaCIub9KKv4= X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2015 11:00:44.0350 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR0301MB1251 Cc: alsa-devel@alsa-project.org, Zidan Wang , Xiubo.Lee@gmail.com, tiwai@suse.com, nicoleotsuka@gmail.com Subject: [alsa-devel] [PATCH] ASoC: fsl_ssi: bclk should never greater than 1/5 IPG clock rate X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP According to the referance menual, the bclk rate must be never greater than 1/5 IPG clock rate. But clkrate is the system clock, afreq is the bit clock. Signed-off-by: Zidan Wang --- sound/soc/fsl/fsl_ssi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index e3abad5..4466bcb 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -677,16 +677,16 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, else clkrate = clk_round_rate(ssi_private->baudclk, tmprate); + clkrate /= factor; + afreq = clkrate / (i + 1); + /* * Hardware limitation: The bclk rate must be * never greater than 1/5 IPG clock rate */ - if (clkrate * 5 > clk_get_rate(ssi_private->clk)) + if (afreq * 5 > clk_get_rate(ssi_private->clk)) continue; - clkrate /= factor; - afreq = clkrate / (i + 1); - if (freq == afreq) sub = 0; else if (freq / afreq == 1)