From patchwork Wed Mar 30 06:57:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AS50 KCHSU0 X-Patchwork-Id: 8692951 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 69DE49F3D1 for ; Wed, 30 Mar 2016 06:57:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 887E12035B for ; Wed, 30 Mar 2016 06:57:24 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 4B47520357 for ; Wed, 30 Mar 2016 06:57:23 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id A4E172617BB; Wed, 30 Mar 2016 08:57:21 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,NO_DNS_FOR_FROM, RCVD_IN_DNSWL_NONE,UNPARSEABLE_RELAY autolearn=no version=3.3.1 Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 0837C2605D4; Wed, 30 Mar 2016 08:57:15 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id D8BC52606F8; Wed, 30 Mar 2016 08:57:12 +0200 (CEST) Received: from maillog.nuvoton.com (maillog.nuvoton.com [202.39.227.15]) by alsa0.perex.cz (Postfix) with ESMTP id A7D3B2605C3 for ; Wed, 30 Mar 2016 08:57:05 +0200 (CEST) Received: from nthcims03.nuvoton.com (nthcims03.nuvoton.com [10.1.8.100]) by maillog.nuvoton.com (Postfix) with ESMTP id 1A0D91C80595; Wed, 30 Mar 2016 14:57:01 +0800 (CST) Received: from localhost.localdomain (10.4.36.27) by nthcims03.nuvoton.com (10.1.8.100) with Microsoft SMTP Server id 8.3.327.1; Wed, 30 Mar 2016 14:57:00 +0800 From: John Hsu To: Date: Wed, 30 Mar 2016 14:57:11 +0800 Message-ID: <1459321031-2365-1-git-send-email-KCHSU0@nuvoton.com> X-Mailer: git-send-email 2.6.4 MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, anatol.pomozov@gmail.com, YHCHuang@nuvoton.com, John Hsu , lgirdwood@gmail.com, benzh@chromium.org, CTLIN0@nuvoton.com, mhkuo@nuvoton.com, yong.zhi@intel.com Subject: [alsa-devel] [PATCH] ASoC: nau8825: assign DAC Ch to match headset L/R X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP The default value of DAC channel select is reverse in codec. For normal usage, switch the channel select when codec bootup. Signed-off-by: John Hsu --- sound/soc/codecs/nau8825.c | 5 +++++ sound/soc/codecs/nau8825.h | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/sound/soc/codecs/nau8825.c b/sound/soc/codecs/nau8825.c index 3e7bee2..1a99a25 100644 --- a/sound/soc/codecs/nau8825.c +++ b/sound/soc/codecs/nau8825.c @@ -905,6 +905,11 @@ static void nau8825_init_regs(struct nau8825 *nau8825) NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK, (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) | (0x3 << NAU8825_RDAC_VREF_SFT)); + /* Config L/R channel */ + regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL, + NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L); + regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL, + NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R); } static const struct regmap_config nau8825_regmap_config = { diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h index 5fe009d..fcf0d0a 100644 --- a/sound/soc/codecs/nau8825.h +++ b/sound/soc/codecs/nau8825.h @@ -256,9 +256,15 @@ /* DACL_CTRL (0x33) */ #define NAU8825_DACL_CH_SEL_SFT 9 +#define NAU8825_DACL_CH_SEL_MASK (0x1 << NAU8825_DACL_CH_SEL_SFT) +#define NAU8825_DACL_CH_SEL_L (0x0 << NAU8825_DACL_CH_SEL_SFT) +#define NAU8825_DACL_CH_SEL_R (0x1 << NAU8825_DACL_CH_SEL_SFT) /* DACR_CTRL (0x34) */ #define NAU8825_DACR_CH_SEL_SFT 9 +#define NAU8825_DACR_CH_SEL_MASK (0x1 << NAU8825_DACR_CH_SEL_SFT) +#define NAU8825_DACR_CH_SEL_L (0x0 << NAU8825_DACR_CH_SEL_SFT) +#define NAU8825_DACR_CH_SEL_R (0x1 << NAU8825_DACR_CH_SEL_SFT) /* CLASSG_CTRL (0x50) */ #define NAU8825_CLASSG_TIMER_SFT 8