From patchwork Tue Jul 19 10:46:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 9238271 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 72506600CB for ; Tue, 19 Jul 2016 20:23:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 63D9D26D19 for ; Tue, 19 Jul 2016 20:23:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 581882756B; Tue, 19 Jul 2016 20:23:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1AC2026D19 for ; Tue, 19 Jul 2016 20:23:45 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id DC223266936; Tue, 19 Jul 2016 22:23:43 +0200 (CEST) Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id B6E0E2661CF; Tue, 19 Jul 2016 18:21:09 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 594142661BF; Tue, 19 Jul 2016 18:21:07 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by alsa0.perex.cz (Postfix) with ESMTP id F13C3266052 for ; Tue, 19 Jul 2016 12:39:38 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 19 Jul 2016 03:39:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.28,389,1464678000"; d="scan'208"; a="1019685681" Received: from vkoul-udesk7.iind.intel.com ([10.223.84.143]) by orsmga002.jf.intel.com with ESMTP; 19 Jul 2016 03:39:35 -0700 From: Vinod Koul To: alsa-devel@alsa-project.org Date: Tue, 19 Jul 2016 16:16:42 +0530 Message-Id: <1468925202-29445-3-git-send-email-vinod.koul@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1468925202-29445-1-git-send-email-vinod.koul@intel.com> References: <1468925202-29445-1-git-send-email-vinod.koul@intel.com> MIME-Version: 1.0 Cc: tiwai@suse.de, Hardik T Shah , Guneshwor Singh , liam.r.girdwood@linux.intel.com, patches.audio@intel.com, broonie@kernel.org, Vinod Koul Subject: [alsa-devel] [PATCH v2 2/2] ALSA - hda: Add support for link audio time reporting X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Guneshwor Singh The HDA controller from SKL onwards support additional timestamp reporting of the link time. The link time is read from HW registers and converted to audio values. Signed-off-by: Guneshwor Singh Signed-off-by: Hardik T Shah Signed-off-by: Vinod Koul --- sound/pci/hda/hda_controller.c | 195 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 194 insertions(+), 1 deletion(-) diff --git a/sound/pci/hda/hda_controller.c b/sound/pci/hda/hda_controller.c index 7e5e4c261e51..9ae69c000a13 100644 --- a/sound/pci/hda/hda_controller.c +++ b/sound/pci/hda/hda_controller.c @@ -27,6 +27,12 @@ #include #include #include + +#ifdef CONFIG_X86 +/* for art-tsc conversion */ +#include +#endif + #include #include #include "hda_controller.h" @@ -337,12 +343,169 @@ static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream) azx_get_position(chip, azx_dev)); } +/* + * azx_scale64: Scale base by mult/div while not overflowing sanely + * + * Derived from scale64_check_overflow in kernel/time/timekeeping.c + * + * The tmestamps for a 48Khz stream can overflow after (2^64/10^9)/48K which + * is about 384307 ie ~4.5 days. + * + * This scales the calculation so that overflow will happen but after 2^64 / + * 48000 secs, which is pretty large! + * + * In caln below: + * base may overflow, but since there isn’t any additional division + * performed on base it’s OK + * rem can’t overflow because both are 32-bit values + */ + +#ifdef CONFIG_X86 +static u64 azx_scale64(u64 base, u32 num, u32 den) +{ + u64 rem; + + rem = do_div(base, den); + + base *= num; + rem *= num; + + do_div(rem, den); + + return base + rem; +} + +static int azx_get_sync_time(ktime_t *device, + struct system_counterval_t *system, void *ctx) +{ + struct snd_pcm_substream *substream = (struct snd_pcm_substream *)ctx; + struct azx_dev *azx_dev = get_azx_dev(substream); + struct azx_pcm *apcm = snd_pcm_substream_chip(substream); + struct azx *chip = apcm->chip; + struct snd_pcm_runtime *runtime; + u64 ll_counter, ll_counter_l, ll_counter_h; + u64 tsc_counter, tsc_counter_l, tsc_counter_h; + u32 wallclk_ctr, wallclk_cycles; + bool direction; + u32 dma_select; + u32 timeout = 200; + u32 retry_count = 0; + + runtime = substream->runtime; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + direction = 1; + else + direction = 0; + + /* 0th stream tag is not used, so DMA ch 0 is for 1st stream tag */ + do { + timeout = 100; + dma_select = (direction << GTSCC_CDMAS_DMA_DIR_SHIFT) | + (azx_dev->core.stream_tag - 1); + _snd_hdac_chip_write(l, azx_bus(chip), AZX_REG_GTSCC, + dma_select); + /* Enable the capture */ + _snd_hdac_chip_write(l, azx_bus(chip), AZX_REG_GTSCC, + _snd_hdac_chip_read(l, azx_bus(chip), + AZX_REG_GTSCC) | GTSCC_TSCCI_MASK); + + while (timeout) { + if (_snd_hdac_chip_read(l, azx_bus(chip), + AZX_REG_GTSCC) & GTSCC_TSCCD_MASK) + break; + timeout--; + } + + if (!timeout) { + dev_err(chip->card->dev, "GTSCC capture Timedout!\n"); + return -EIO; + } + + /* Read wall clock counter */ + wallclk_ctr = _snd_hdac_chip_read(l, azx_bus(chip), + AZX_REG_WALFCC); + + /* Read TSC counter */ + tsc_counter_l = _snd_hdac_chip_read(l, azx_bus(chip), + AZX_REG_TSCCL); + tsc_counter_h = _snd_hdac_chip_read(l, azx_bus(chip), + AZX_REG_TSCCU); + + /* Read Link counter */ + ll_counter_l = _snd_hdac_chip_read(l, azx_bus(chip), + AZX_REG_LLPCL); + ll_counter_h = _snd_hdac_chip_read(l, azx_bus(chip), + AZX_REG_LLPCU); + + /* Ack: registers read done */ + _snd_hdac_chip_write(l, azx_bus(chip), + AZX_REG_GTSCC, + (0x1 << GTSCC_TSCCD_SHIFT)); + + tsc_counter = (tsc_counter_h << TSCCU_CCU_SHIFT) | + tsc_counter_l; + + ll_counter = (ll_counter_h << LLPC_CCU_SHIFT) | ll_counter_l; + wallclk_cycles = wallclk_ctr & WALFCC_CIF_MASK; + + /* + * An error occurs near frame "rollover". The clocks in + * frame value indicates whether this error may have + * occurred. Here we use the value of 10 i.e., + * HDA_MAX_CYCLE_OFFSET + */ + if (wallclk_cycles < HDA_MAX_CYCLE_VALUE - HDA_MAX_CYCLE_OFFSET + && wallclk_cycles > HDA_MAX_CYCLE_OFFSET) + break; + + /* + * Sleep before we read again, else we may again get + * value near to MAX_CYCLE. Try to sleep for different + * amount of time so we dont hit the same number again + */ + udelay(retry_count++); + + } while (retry_count != HDA_MAX_CYCLE_READ_RETRY); + + if (retry_count == HDA_MAX_CYCLE_READ_RETRY) { + dev_err(chip->card->dev, "Error in WALFCC cycle count\n"); + return -EIO; + } + + *device = ns_to_ktime(azx_scale64(ll_counter, + NSEC_PER_SEC, runtime->rate)); + *device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) / + ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate)); + + *system = convert_art_to_tsc(tsc_counter); + + return 0; +} + +#else +static int azx_get_sync_time(ktime_t *device, + struct system_counterval_t *system, void *ctx) +{ + return -ENXIO; +} +#endif + +static int azx_get_crosststamp(struct snd_pcm_substream *substream, + struct system_device_crosststamp *xtstamp) +{ + return get_device_system_crosststamp(azx_get_sync_time, + substream, NULL, xtstamp); +} + static int azx_get_time_info(struct snd_pcm_substream *substream, struct timespec *system_ts, struct timespec *audio_ts, struct snd_pcm_audio_tstamp_config *audio_tstamp_config, struct snd_pcm_audio_tstamp_report *audio_tstamp_report) { struct azx_dev *azx_dev = get_azx_dev(substream); + struct snd_pcm_runtime *runtime = substream->runtime; + struct system_device_crosststamp xtstamp; u64 nsec; if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) && @@ -361,8 +524,38 @@ static int azx_get_time_info(struct snd_pcm_substream *substream, audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */ audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */ - } else + } else if ((runtime->hw.info & + SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME) && + (audio_tstamp_config->type_requested == + SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED)) { + + azx_get_crosststamp(substream, &xtstamp); + + switch (runtime->tstamp_type) { + case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC: + return -EINVAL; + + case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW: + *system_ts = ktime_to_timespec(xtstamp.sys_monoraw); + break; + + default: + *system_ts = ktime_to_timespec(xtstamp.sys_realtime); + break; + + } + + *audio_ts = ktime_to_timespec(xtstamp.device); + + audio_tstamp_report->actual_type = + SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED; + audio_tstamp_report->accuracy_report = 1; + /* 24 MHz WallClock == 42ns resolution */ + audio_tstamp_report->accuracy = 42; + + } else { audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT; + } return 0; }