| Message ID | 1491477501-12379-1-git-send-email-libin.yang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, 06 Apr 2017 13:18:20 +0200, libin.yang@intel.com wrote: > > From: Libin Yang <libin.yang@intel.com> > > This patch refines the definition of AZX_MLCTL_SPA and AZX_MLCTL_CPA > and add more definitions of ML registers > > Signed-off-by: Libin Yang <libin.yang@intel.com> Applied, thanks. Takashi > --- > include/sound/hda_register.h | 8 +++++--- > sound/hda/ext/hdac_ext_controller.c | 6 +++--- > 2 files changed, 8 insertions(+), 6 deletions(-) > > diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h > index 0013063..8df12e4 100644 > --- a/include/sound/hda_register.h > +++ b/include/sound/hda_register.h > @@ -243,9 +243,11 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; > #define AZX_REG_ML_LOUTPAY 0x20 > #define AZX_REG_ML_LINPAY 0x30 > > -#define AZX_MLCTL_SPA (1<<16) > -#define AZX_MLCTL_CPA 23 > - > +#define ML_LCTL_SCF_MASK 0xF > +#define AZX_MLCTL_SPA (0x1 << 16) > +#define AZX_MLCTL_CPA (0x1 << 23) > +#define AZX_MLCTL_SPA_SHIFT 16 > +#define AZX_MLCTL_CPA_SHIFT 23 > > /* registers for DMA Resume Capability Structure */ > #define AZX_DRSM_CAP_ID 0x5 > diff --git a/sound/hda/ext/hdac_ext_controller.c b/sound/hda/ext/hdac_ext_controller.c > index 2614691..84f3b81 100644 > --- a/sound/hda/ext/hdac_ext_controller.c > +++ b/sound/hda/ext/hdac_ext_controller.c > @@ -171,7 +171,7 @@ static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable) > { > int timeout; > u32 val; > - int mask = (1 << AZX_MLCTL_CPA); > + int mask = (1 << AZX_MLCTL_CPA_SHIFT); > > udelay(3); > timeout = 150; > @@ -179,10 +179,10 @@ static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable) > do { > val = readl(link->ml_addr + AZX_REG_ML_LCTL); > if (enable) { > - if (((val & mask) >> AZX_MLCTL_CPA)) > + if (((val & mask) >> AZX_MLCTL_CPA_SHIFT)) > return 0; > } else { > - if (!((val & mask) >> AZX_MLCTL_CPA)) > + if (!((val & mask) >> AZX_MLCTL_CPA_SHIFT)) > return 0; > } > udelay(3); > -- > 2.7.4 >
diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h index 0013063..8df12e4 100644 --- a/include/sound/hda_register.h +++ b/include/sound/hda_register.h @@ -243,9 +243,11 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define AZX_REG_ML_LOUTPAY 0x20 #define AZX_REG_ML_LINPAY 0x30 -#define AZX_MLCTL_SPA (1<<16) -#define AZX_MLCTL_CPA 23 - +#define ML_LCTL_SCF_MASK 0xF +#define AZX_MLCTL_SPA (0x1 << 16) +#define AZX_MLCTL_CPA (0x1 << 23) +#define AZX_MLCTL_SPA_SHIFT 16 +#define AZX_MLCTL_CPA_SHIFT 23 /* registers for DMA Resume Capability Structure */ #define AZX_DRSM_CAP_ID 0x5 diff --git a/sound/hda/ext/hdac_ext_controller.c b/sound/hda/ext/hdac_ext_controller.c index 2614691..84f3b81 100644 --- a/sound/hda/ext/hdac_ext_controller.c +++ b/sound/hda/ext/hdac_ext_controller.c @@ -171,7 +171,7 @@ static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable) { int timeout; u32 val; - int mask = (1 << AZX_MLCTL_CPA); + int mask = (1 << AZX_MLCTL_CPA_SHIFT); udelay(3); timeout = 150; @@ -179,10 +179,10 @@ static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable) do { val = readl(link->ml_addr + AZX_REG_ML_LCTL); if (enable) { - if (((val & mask) >> AZX_MLCTL_CPA)) + if (((val & mask) >> AZX_MLCTL_CPA_SHIFT)) return 0; } else { - if (!((val & mask) >> AZX_MLCTL_CPA)) + if (!((val & mask) >> AZX_MLCTL_CPA_SHIFT)) return 0; } udelay(3);