From patchwork Thu Jan 10 17:03:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 10756689 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 283AA14E5 for ; Thu, 10 Jan 2019 19:33:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1643129AE9 for ; Thu, 10 Jan 2019 19:33:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0A9CF29AEA; Thu, 10 Jan 2019 19:33:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0FFAB29AF2 for ; Thu, 10 Jan 2019 19:33:32 +0000 (UTC) Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id B5F31267558; Thu, 10 Jan 2019 18:03:59 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 878F826755C; Thu, 10 Jan 2019 18:03:57 +0100 (CET) Received: from hqemgate15.nvidia.com (hqemgate15.nvidia.com [216.228.121.64]) by alsa0.perex.cz (Postfix) with ESMTP id 2CF1B267548 for ; Thu, 10 Jan 2019 18:03:53 +0100 (CET) Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 10 Jan 2019 09:03:34 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 10 Jan 2019 09:03:52 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 10 Jan 2019 09:03:52 -0800 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 10 Jan 2019 17:03:51 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 10 Jan 2019 17:03:51 +0000 Received: from linux.nvidia.com (Not Verified[10.24.34.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 10 Jan 2019 09:03:51 -0800 From: Sameer Pujar To: , , Date: Thu, 10 Jan 2019 22:33:23 +0530 Message-ID: <1547139805-1904-3-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1547139805-1904-1-git-send-email-spujar@nvidia.com> References: <1547139805-1904-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1547139814; bh=/OagevhRj/UYaT/jm6A/+wY/rGgtuJ/+Ux0MNnFYh+8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=YlIYywNXh7UP0C7b9q49IPZUdgiAabXHwEfMTOAlcZLwfNjxLQwWQw2yeWQfgbtnf qJ1z84y8c+bywBiF2UHLPhz7PzGhsuMKIbfnRRMNzFizWLjSgCXUr6PWRgvC9Vtk1Z snilfvF6I0/Dwrb2KLlitwn41n1MkaAX3OjQzY4UrAYtTs/PIA0yrZ7m2gT+nhS/hx 52BoWRySQ//67PwFYYCSoDoGaKxDH7mZo6RdwQa1qAa6G94oR5gFqG3LUiCtM4XK1X pbHCjcL+vVAmhu8AINMZIK/CRdj/InHDIKGJvvWncGToOWj7tk0oQ0n5qpAF6eVpq3 tBb7QiUrgzmaw== Cc: alsa-devel@alsa-project.org, Sameer Pujar Subject: [alsa-devel] [PATCH 3/5] ALSA: hda: add register offset for stripe control X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP bits 16:17 in SD_CTL register refer to stripe control. Added an offset register(AZX_REG_SD_CTL_3B) to have exclusive read/write of corresponding register byte. This helps to avoid unnecessary 32-bit read/write of SD_CTL whenever only stripe or other bits of corresponding byte need to be updated. Also HD audio spec defines SD_CTL as 3 byte register. Signed-off-by: Sameer Pujar Reviewed-by: Mohan Kumar D Reviewed-by: Ravindra Lokhande --- include/sound/hda_register.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h index 2ab39fb..5b1f5d8 100644 --- a/include/sound/hda_register.h +++ b/include/sound/hda_register.h @@ -79,6 +79,7 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; /* stream register offsets from stream base */ #define AZX_REG_SD_CTL 0x00 +#define AZX_REG_SD_CTL_3B 0x02 /* 3rd byte of SD_CTL register */ #define AZX_REG_SD_STS 0x03 #define AZX_REG_SD_LPIB 0x04 #define AZX_REG_SD_CBL 0x08