From patchwork Fri Jan 11 17:22:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sameer Pujar X-Patchwork-Id: 10760367 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5342D1515 for ; Fri, 11 Jan 2019 17:22:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 322862A238 for ; Fri, 11 Jan 2019 17:22:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2632D2A27A; Fri, 11 Jan 2019 17:22:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6871C2A24D for ; Fri, 11 Jan 2019 17:22:57 +0000 (UTC) Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 4D9B7267993; Fri, 11 Jan 2019 18:22:45 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id CBF1026799A; Fri, 11 Jan 2019 18:22:42 +0100 (CET) Received: from hqemgate16.nvidia.com (hqemgate16.nvidia.com [216.228.121.65]) by alsa0.perex.cz (Postfix) with ESMTP id 9D3A726797E for ; Fri, 11 Jan 2019 18:22:40 +0100 (CET) Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 11 Jan 2019 09:22:13 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 11 Jan 2019 09:22:39 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 11 Jan 2019 09:22:39 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 11 Jan 2019 17:22:39 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Fri, 11 Jan 2019 17:22:39 +0000 Received: from linux.nvidia.com (Not Verified[10.24.34.185]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 11 Jan 2019 09:22:38 -0800 From: Sameer Pujar To: , , Date: Fri, 11 Jan 2019 22:52:06 +0530 Message-ID: <1547227328-32558-4-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1547227328-32558-1-git-send-email-spujar@nvidia.com> References: <1547227328-32558-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1547227333; bh=tNcd1azEnfJXvtAit7/4BYUhmT+gulyezUbvR2gGSC4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=ICHOSOLXNFkTTQzvo6tq2zB/NUYW396DjP73z/7Ur1Aw9E+XcaabmhiKaStBJ8x4U XAsTHFNrhlYgsS6JMKPe0TBoqB1b/S/Kk8Vm3PA+dPzBIR4S2biojYKf5ABrEJRgDU IlS4XYdLafBDgDqXE/BgGTDTG3G2Nc9PkxjZa+PR8HQDurBRVuzXetAFDWJhP22ya/ b5HGrU1pima3ECU92cXgrLA/sUjklhD47qrPcjiC+wV2c5Uqoz11o3NSCYBwrVMw0X rFQuA7exCN1kIO54JitQ1OxNDZSBFAcSxUNX+f+BBEfic+m/zlXzrJDwMhVrnvwLkU +aeD9MDpACe6g== Cc: alsa-devel@alsa-project.org, Sameer Pujar Subject: [alsa-devel] [PATCH v2 3/5] ALSA: hda: add register offset for stripe control X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP bits 16:17 in SD_CTL register refer to stripe control. Added an offset register(AZX_REG_SD_CTL_3B) to have exclusive read/write of corresponding register byte. This helps to avoid unnecessary 32-bit read/write of SD_CTL whenever only stripe or other bits of corresponding byte need to be updated. Also HD audio spec defines SD_CTL as 3 byte register. SD_CTL_STRIPE_MASK(0x3) can be used for stripe control programming and when updating AZX_REG_SD_CTL_3B. Signed-off-by: Sameer Pujar Reviewed-by: Mohan Kumar D Reviewed-by: Ravindra Lokhande --- include/sound/hda_register.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h index 2ab39fb..0fd3929 100644 --- a/include/sound/hda_register.h +++ b/include/sound/hda_register.h @@ -79,6 +79,7 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; /* stream register offsets from stream base */ #define AZX_REG_SD_CTL 0x00 +#define AZX_REG_SD_CTL_3B 0x02 /* 3rd byte of SD_CTL register */ #define AZX_REG_SD_STS 0x03 #define AZX_REG_SD_LPIB 0x04 #define AZX_REG_SD_CBL 0x08 @@ -165,6 +166,7 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; #define SD_INT_COMPLETE 0x04 /* completion interrupt */ #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ SD_INT_COMPLETE) +#define SD_CTL_STRIPE_MASK 0x3 /* stripe control mask */ /* SD_STS */ #define SD_STS_FIFO_READY 0x20 /* FIFO ready */