Message ID | 1591938925-1070-5-git-send-email-derek.fang@realtek.com (mailing list archive) |
---|---|
State | Accepted |
Commit | 19ab0f005b165146ea4a93f71e9cb5e71de9c0ce |
Headers | show |
Series | [1/5] ASoC: rt5682: Enable Vref2 under using PLL2 | expand |
diff --git a/sound/soc/codecs/rt5682.c b/sound/soc/codecs/rt5682.c index f9d8d8c..ff6a5bb 100644 --- a/sound/soc/codecs/rt5682.c +++ b/sound/soc/codecs/rt5682.c @@ -2859,12 +2859,13 @@ static int rt5682_probe(struct snd_soc_component *component) return ret; } rt5682->mclk = NULL; - } else { - /* Register CCF DAI clock control */ - ret = rt5682_register_dai_clks(component); - if (ret) - return ret; } + + /* Register CCF DAI clock control */ + ret = rt5682_register_dai_clks(component); + if (ret) + return ret; + /* Initial setup for CCF */ rt5682->lrck[RT5682_AIF1] = CLK_48; #endif