new file mode 100644
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/nvidia,tegra186-dspk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra186 DSPK Controller Device Tree Bindings
+
+description: |
+ The Digital Speaker Controller (DSPK) can be viewed as a Pulse
+ Density Modulation (PDM) transmitter that up-samples the input to
+ the desired sampling rate by interpolation and then converts the
+ over sampled Pulse Code Modulation (PCM) input to the desired 1-bit
+ output via Delta Sigma Modulation (DSM).
+
+maintainers:
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Sameer Pujar <spujar@nvidia.com>
+
+properties:
+ $nodename:
+ pattern: "^dspk@[0-9a-f]*$"
+
+ compatible:
+ oneOf:
+ - const: nvidia,tegra186-dspk
+ - items:
+ - const: nvidia,tegra194-dspk
+ - const: nvidia,tegra186-dspk
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: dspk
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
+ assigned-clock-rates:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 1
+
+ sound-name-prefix:
+ pattern: "^DSPK[1-9]$"
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/string
+ description:
+ Used as prefix for sink/source names of the component. Must be a
+ unique string among multiple instances of the same component.
+ The name can be "DSPK1" or "DSPKx", where x depends on the maximum
+ available instances on a Tegra SoC.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-parents
+ - "#sound-dai-cells"
+ - sound-name-prefix
+
+examples:
+ - |
+ #include<dt-bindings/clock/tegra186-clock.h>
+
+ dspk@2905000 {
+ compatible = "nvidia,tegra186-dspk";
+ reg = <0x2905000 0x100>;
+ clocks = <&bpmp TEGRA186_CLK_DSPK1>;
+ clock-names = "dspk";
+ assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
+ assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
+ assigned-clock-rates = <12288000>;
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "DSPK1";
+ };
+
+...
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra210 ADMAIF Device Tree Bindings
+
+description: |
+ ADMAIF is the interface between ADMA and AHUB. Each ADMA channel
+ that sends/receives data to/from AHUB must interface through an
+ ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF
+ Tx channel and ADMA channel receiving data from AHUB pairs with
+ ADMAIF Rx channel.
+
+maintainers:
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Sameer Pujar <spujar@nvidia.com>
+
+properties:
+ $nodename:
+ pattern: "^admaif@[0-9a-f]*$"
+
+ compatible:
+ oneOf:
+ - enum:
+ - nvidia,tegra210-admaif
+ - nvidia,tegra186-admaif
+ - items:
+ - const: nvidia,tegra194-admaif
+ - const: nvidia,tegra186-admaif
+
+ reg:
+ maxItems: 1
+
+ dmas: true
+
+ dma-names: true
+
+ "#sound-dai-cells":
+ const: 1
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra210-admaif
+
+then:
+ properties:
+ dmas:
+ description:
+ DMA channel specifiers, equally divided for Tx and Rx.
+ minItems: 1
+ maxItems: 20
+ dma-names:
+ items:
+ pattern: "^[rt]x(10|[1-9])$"
+ description:
+ Should be "rx1", "rx2" ... "rx10" for DMA Rx channel
+ Should be "tx1", "tx2" ... "tx10" for DMA Tx channel
+ minItems: 1
+ maxItems: 20
+
+else:
+ properties:
+ dmas:
+ description:
+ DMA channel specifiers, equally divided for Tx and Rx.
+ minItems: 1
+ maxItems: 40
+ dma-names:
+ items:
+ pattern: "^[rt]x(1[0-9]|[1-9]|20)$"
+ description:
+ Should be "rx1", "rx2" ... "rx20" for DMA Rx channel
+ Should be "tx1", "tx2" ... "tx20" for DMA Tx channel
+ minItems: 1
+ maxItems: 40
+
+required:
+ - compatible
+ - reg
+ - dmas
+ - dma-names
+ - "#sound-dai-cells"
+
+examples:
+ - |
+ admaif@702d0000 {
+ compatible = "nvidia,tegra210-admaif";
+ reg = <0x702d0000 0x800>;
+ dmas = <&adma 1>, <&adma 1>,
+ <&adma 2>, <&adma 2>,
+ <&adma 3>, <&adma 3>,
+ <&adma 4>, <&adma 4>,
+ <&adma 5>, <&adma 5>,
+ <&adma 6>, <&adma 6>,
+ <&adma 7>, <&adma 7>,
+ <&adma 8>, <&adma 8>,
+ <&adma 9>, <&adma 9>,
+ <&adma 10>, <&adma 10>;
+ dma-names = "rx1", "tx1",
+ "rx2", "tx2",
+ "rx3", "tx3",
+ "rx4", "tx4",
+ "rx5", "tx5",
+ "rx6", "tx6",
+ "rx7", "tx7",
+ "rx8", "tx8",
+ "rx9", "tx9",
+ "rx10", "tx10";
+ #sound-dai-cells = <1>;
+ };
+
+...
new file mode 100644
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra210 AHUB Device Tree Bindings
+
+description: |
+ The Audio Hub (AHUB) comprises a collection of hardware accelerators
+ for audio pre-processing, post-processing and a programmable full
+ crossbar for routing audio data across these accelerators. It has
+ external interfaces such as I2S, DMIC, DSPK. It interfaces with ADMA
+ engine through ADMAIF.
+
+maintainers:
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Sameer Pujar <spujar@nvidia.com>
+
+properties:
+ $nodename:
+ pattern: "^ahub@[0-9a-f]*$"
+
+ compatible:
+ oneOf:
+ - enum:
+ - nvidia,tegra210-ahub
+ - nvidia,tegra186-ahub
+ - items:
+ - const: nvidia,tegra194-ahub
+ - const: nvidia,tegra186-ahub
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: ahub
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
+ assigned-clock-rates:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+ "#sound-dai-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-parents
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - "#sound-dai-cells"
+
+examples:
+ - |
+ #include<dt-bindings/clock/tegra210-car.h>
+
+ ahub@702d0800 {
+ compatible = "nvidia,tegra210-ahub";
+ reg = <0x702d0800 0x800>;
+ clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
+ clock-names = "ahub";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x702d0000 0x702d0000 0x0000e400>;
+ #sound-dai-cells = <1>;
+
+ // All AHUB child nodes below
+ admaif@702d0000 {
+ compatible = "nvidia,tegra210-admaif";
+ reg = <0x702d0000 0x800>;
+ dmas = <&adma 1>, <&adma 1>,
+ <&adma 2>, <&adma 2>,
+ <&adma 3>, <&adma 3>,
+ <&adma 4>, <&adma 4>,
+ <&adma 5>, <&adma 5>,
+ <&adma 6>, <&adma 6>,
+ <&adma 7>, <&adma 7>,
+ <&adma 8>, <&adma 8>,
+ <&adma 9>, <&adma 9>,
+ <&adma 10>, <&adma 10>;
+ dma-names = "rx1", "tx1",
+ "rx2", "tx2",
+ "rx3", "tx3",
+ "rx4", "tx4",
+ "rx5", "tx5",
+ "rx6", "tx6",
+ "rx7", "tx7",
+ "rx8", "tx8",
+ "rx9", "tx9",
+ "rx10", "tx10";
+ #sound-dai-cells = <1>;
+ };
+
+ i2s@702d1000 {
+ compatible = "nvidia,tegra210-i2s";
+ reg = <0x702d1000 0x100>;
+ clocks = <&tegra_car TEGRA210_CLK_I2S0>;
+ clock-names = "i2s";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ assigned-clock-rates = <1536000>;
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "I2S1";
+ };
+
+ dmic@702d4000 {
+ compatible = "nvidia,tegra210-dmic";
+ reg = <0x702d4000 0x100>;
+ clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
+ clock-names = "dmic";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ assigned-clock-rates = <3072000>;
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "DMIC1";
+ };
+
+ // More child nodes to follow
+ };
+
+...
new file mode 100644
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/nvidia,tegra210-dmic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra210 DMIC Controller Device Tree Bindings
+
+description: |
+ The Digital MIC (DMIC) Controller is used to interface with Pulse
+ Density Modulation (PDM) input devices. It converts PDM signals to
+ Pulse Coded Modulation (PCM) signals. DMIC can be viewed as a PDM
+ receiver.
+
+maintainers:
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Sameer Pujar <spujar@nvidia.com>
+
+properties:
+ $nodename:
+ pattern: "^dmic@[0-9a-f]*$"
+
+ compatible:
+ oneOf:
+ - const: nvidia,tegra210-dmic
+ - items:
+ - enum:
+ - nvidia,tegra194-dmic
+ - nvidia,tegra186-dmic
+ - const: nvidia,tegra210-dmic
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: dmic
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
+ assigned-clock-rates:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 1
+
+ sound-name-prefix:
+ pattern: "^DMIC[1-9]$"
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/string
+ description:
+ used as prefix for sink/source names of the component. Must be a
+ unique string among multiple instances of the same component.
+ The name can be "DMIC1" or "DMIC2" ... "DMICx", where x depends
+ on the maximum available instances on a Tegra SoC.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-parents
+ - "#sound-dai-cells"
+
+examples:
+ - |
+ #include<dt-bindings/clock/tegra210-car.h>
+
+ dmic@702d4000 {
+ compatible = "nvidia,tegra210-dmic";
+ reg = <0x702d4000 0x100>;
+ clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
+ clock-names = "dmic";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ assigned-clock-rates = <3072000>;
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "DMIC1";
+ };
+
+...
new file mode 100644
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/nvidia,tegra210-i2s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra210 I2S Controller Device Tree Bindings
+
+description: |
+ The Inter-IC Sound (I2S) controller implements full-duplex,
+ bi-directional and single direction point-to-point serial
+ interfaces. It can interface with I2S compatible devices.
+ I2S controller can operate both in master and slave mode.
+
+maintainers:
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Sameer Pujar <spujar@nvidia.com>
+
+properties:
+ $nodename:
+ pattern: "^i2s@[0-9a-f]*$"
+
+ compatible:
+ oneOf:
+ - const: nvidia,tegra210-i2s
+ - items:
+ - enum:
+ - nvidia,tegra194-i2s
+ - nvidia,tegra186-i2s
+ - const: nvidia,tegra210-i2s
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: I2S bit clock
+ - description:
+ Sync input clock, which can act as clock source to other I/O
+ modules in AHUB. The Tegra I2S driver sets this clock rate as
+ per bit clock rate. I/O module which wants to use this clock
+ as source, can mention this clock as parent in the DT bindings.
+ This is an optional clock entry, since it is only required when
+ some other I/O wants to reference from a particular I2Sx
+ instance.
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: i2s
+ - const: sync_input
+
+ assigned-clocks:
+ minItems: 1
+ maxItems: 2
+
+ assigned-clock-parents:
+ minItems: 1
+ maxItems: 2
+
+ assigned-clock-rates:
+ minItems: 1
+ maxItems: 2
+
+ "#sound-dai-cells":
+ const: 1
+
+ sound-name-prefix:
+ pattern: "^I2S[1-9]$"
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/string
+ description:
+ Used as prefix for sink/source names of the component. Must be a
+ unique string among multiple instances of the same component.
+ The name can be "I2S1" or "I2S2" ... "I2Sx", where x depends
+ on the maximum available instances on a Tegra SoC.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - assigned-clocks
+ - assigned-clock-parents
+ - "#sound-dai-cells"
+
+examples:
+ - |
+ #include<dt-bindings/clock/tegra210-car.h>
+
+ i2s@702d1000 {
+ compatible = "nvidia,tegra210-i2s";
+ reg = <0x702d1000 0x100>;
+ clocks = <&tegra_car TEGRA210_CLK_I2S0>;
+ clock-names = "i2s";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ assigned-clock-rates = <1536000>;
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "I2S1";
+ };
+
+...
This patch adds YAML schema for DT binding of AHUB and few of its following components. These devices will be registered as ASoC components and binding will be used on Tegra210 and later chips. * ADMAIF * I2S * DMIC * DSPK Signed-off-by: Sameer Pujar <spujar@nvidia.com> --- .../bindings/sound/nvidia,tegra186-dspk.yaml | 88 +++++++++++++ .../bindings/sound/nvidia,tegra210-admaif.yaml | 116 +++++++++++++++++ .../bindings/sound/nvidia,tegra210-ahub.yaml | 144 +++++++++++++++++++++ .../bindings/sound/nvidia,tegra210-dmic.yaml | 88 +++++++++++++ .../bindings/sound/nvidia,tegra210-i2s.yaml | 106 +++++++++++++++ 5 files changed, 542 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/nvidia,tegra186-dspk.yaml create mode 100644 Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml create mode 100644 Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml create mode 100644 Documentation/devicetree/bindings/sound/nvidia,tegra210-dmic.yaml create mode 100644 Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml