@@ -29,6 +29,10 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle
description: The phandle of the mediatek topckgen controller
+ mediatek,infracfg:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The phandle of the mediatek infracfg controller
+
power-domains:
maxItems: 1
@@ -52,6 +56,7 @@ properties:
- description: mux for i2si1_mck
- description: mux for i2si2_mck
- description: audio 26m clock
+ - description: audio pll1 divide 4
clock-names:
items:
@@ -73,6 +78,7 @@ properties:
- const: i2si1_m_sel
- const: i2si2_m_sel
- const: adsp_audio_26m
+ - const: apll1_d4
mediatek,etdm-in1-cowork-source:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -147,6 +153,8 @@ required:
- power-domains
- clocks
- clock-names
+ - assigned-clocks
+ - assigned-clock-parents
additionalProperties: false
@@ -184,7 +192,8 @@ examples:
<&topckgen 78>, //CLK_TOP_I2SO2
<&topckgen 79>, //CLK_TOP_I2SI1
<&topckgen 80>, //CLK_TOP_I2SI2
- <&adsp_audio26m 0>; //CLK_AUDIODSP_AUDIO26M
+ <&adsp_audio26m 0>, //CLK_AUDIODSP_AUDIO26M
+ <&topckgen 136>; //CLK_TOP_APLL1_D4
clock-names = "clk26m",
"apll1",
"apll2",
@@ -202,7 +211,10 @@ examples:
"i2so2_m_sel",
"i2si1_m_sel",
"i2si2_m_sel",
- "adsp_audio_26m";
+ "adsp_audio_26m",
+ "apll1_d4";
+ assigned-clocks = <&topckgen 83>; //CLK_TOP_A1SYS_HP
+ assigned-clock-parents = <&clk26m>;
};
...
Assign top_a1sys_hp clock to 26M, and add apll1_d4 to clocks for switching the parent of top_a1sys_hp dynamically On the other hand, "mediatek,infracfg" is included for bus protection. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> --- .../bindings/sound/mediatek,mt8188-afe.yaml | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)