From patchwork Wed Jun 1 17:54:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 9147919 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BFD4260777 for ; Wed, 1 Jun 2016 17:55:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B1893265F9 for ; Wed, 1 Jun 2016 17:55:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A60E726EFF; Wed, 1 Jun 2016 17:55:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DECB8265F9 for ; Wed, 1 Jun 2016 17:55:55 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id AFC14266C87; Wed, 1 Jun 2016 19:55:53 +0200 (CEST) Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id CD5912660C2; Wed, 1 Jun 2016 19:54:46 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 164BB2650C0; Wed, 1 Jun 2016 19:54:44 +0200 (CEST) Received: from mail.free-electrons.com (down.free-electrons.com [37.187.137.238]) by alsa0.perex.cz (Postfix) with ESMTP id 02BFC265317 for ; Wed, 1 Jun 2016 19:54:36 +0200 (CEST) Received: by mail.free-electrons.com (Postfix, from userid 110) id 50CC63D4; Wed, 1 Jun 2016 19:54:35 +0200 (CEST) Received: from localhost (LFbn-1-2034-31.w90-76.abo.wanadoo.fr [90.76.103.31]) by mail.free-electrons.com (Postfix) with ESMTPSA id 0C4B834B; Wed, 1 Jun 2016 19:54:35 +0200 (CEST) From: Maxime Ripard To: Rob Herring , Chen-Yu Tsai , Mark Brown , Liam Girdwood Date: Wed, 1 Jun 2016 19:54:29 +0200 Message-Id: <20160601175430.11625-4-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160601175430.11625-1-maxime.ripard@free-electrons.com> References: <20160601175430.11625-1-maxime.ripard@free-electrons.com> MIME-Version: 1.0 Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, gianfranco@moddevices.com, =?UTF-8?q?Emilio=20L=C3=B3pez?= , linux-kernel@vger.kernel.org, Code Kipper , Andrea Venturi , Maxime Ripard , linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH 3/4] ARM: sun7i: Add mod1 clock nodes X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Emilio López This commit adds all the mod1 clocks available on A20 to its device tree. This list was created by looking at the A20 user manual. Signed-off-by: Emilio López Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun7i-a20.dtsi | 48 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index febdf4c72fb0..603fda5b7f94 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -366,9 +366,9 @@ <5>, <6>, <7>, <8>, <10>; clock-output-names = "apb0_codec", "apb0_spdif", - "apb0_ac97", "apb0_iis0", "apb0_iis1", + "apb0_ac97", "apb0_i2s0", "apb0_i2s1", "apb0_pio", "apb0_ir0", "apb0_ir1", - "apb0_iis2", "apb0_keypad"; + "apb0_i2s2", "apb0_keypad"; }; apb1: clk@01c20058 { @@ -518,6 +518,28 @@ clock-output-names = "ir1"; }; + i2s0_clk: clk@01c200b8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200b8 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "i2s0"; + }; + + ac97_clk: clk@01c200bc { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200bc 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "ac97"; + }; + spdif_clk: clk@01c200c0 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod1-clk"; @@ -555,6 +577,28 @@ clock-output-names = "spi3"; }; + i2s1_clk: clk@01c200d8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200d8 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "i2s1"; + }; + + i2s2_clk: clk@01c200dc { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200dc 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "i2s2"; + }; + dram_gates: clk@01c20100 { #clock-cells = <1>; compatible = "allwinner,sun4i-a10-dram-gates-clk";