diff mbox

[03/17] ASoC: tlv320aic31xx: Fix GPIO1 register definition

Message ID 20171109002741.10897-4-afd@ti.com (mailing list archive)
State New, archived
Headers show

Commit Message

Andrew Davis Nov. 9, 2017, 12:27 a.m. UTC
GPIO1 control register is number 51, fix this here.

Fixes: bafcbfe429eb ("ASoC: tlv320aic31xx: Make the register values human readable")
Signed-off-by: Andrew F. Davis <afd@ti.com>
---
 sound/soc/codecs/tlv320aic31xx.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Mark Brown Nov. 9, 2017, 12:45 p.m. UTC | #1
On Wed, Nov 08, 2017 at 06:27:27PM -0600, Andrew F. Davis wrote:
> GPIO1 control register is number 51, fix this here.
> 
> Fixes: bafcbfe429eb ("ASoC: tlv320aic31xx: Make the register values human readable")
> Signed-off-by: Andrew F. Davis <afd@ti.com>
> ---

We should send this as a bug fix to stable but this depends on your
reformatting :(
Andrew Davis Nov. 9, 2017, 2:32 p.m. UTC | #2
On 11/09/2017 06:45 AM, Mark Brown wrote:
> On Wed, Nov 08, 2017 at 06:27:27PM -0600, Andrew F. Davis wrote:
>> GPIO1 control register is number 51, fix this here.
>>
>> Fixes: bafcbfe429eb ("ASoC: tlv320aic31xx: Make the register values human readable")
>> Signed-off-by: Andrew F. Davis <afd@ti.com>
>> ---
> 
> We should send this as a bug fix to stable but this depends on your
> reformatting :(
> 

I put it after the reformatting as an example of its value, now that you
have seen it, I'll move it before the reformatting so it can be taken
independently.
diff mbox

Patch

diff --git a/sound/soc/codecs/tlv320aic31xx.h b/sound/soc/codecs/tlv320aic31xx.h
index db95eeae966b..4f126cd82add 100644
--- a/sound/soc/codecs/tlv320aic31xx.h
+++ b/sound/soc/codecs/tlv320aic31xx.h
@@ -82,7 +82,7 @@  struct aic31xx_pdata {
 #define AIC31XX_INTRADCFLAG2	AIC31XX_REG(0, 47) /* ADC Interrupt flags 2 */
 #define AIC31XX_INT1CTRL	AIC31XX_REG(0, 48) /* INT1 interrupt control */
 #define AIC31XX_INT2CTRL	AIC31XX_REG(0, 49) /* INT2 interrupt control */
-#define AIC31XX_GPIO1		AIC31XX_REG(0, 50) /* GPIO1 control */
+#define AIC31XX_GPIO1		AIC31XX_REG(0, 51) /* GPIO1 control */
 #define AIC31XX_DACPRB		AIC31XX_REG(0, 60)
 #define AIC31XX_ADCPRB		AIC31XX_REG(0, 61) /* ADC Instruction Set Register */
 #define AIC31XX_DACSETUP	AIC31XX_REG(0, 63) /* DAC channel setup register */