From patchwork Thu Dec 7 15:38:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 10099565 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D596B605BD for ; Thu, 7 Dec 2017 15:51:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C419626419 for ; Thu, 7 Dec 2017 15:51:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B89A72679B; Thu, 7 Dec 2017 15:51:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_NONE,T_DKIM_INVALID autolearn=no version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C49BD269E2 for ; Thu, 7 Dec 2017 15:51:19 +0000 (UTC) Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 00DF0267B4D; Thu, 7 Dec 2017 16:39:23 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 002A62671A3; Thu, 7 Dec 2017 16:39:09 +0100 (CET) Received: from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17]) by alsa0.perex.cz (Postfix) with ESMTP id 1DE272671D8 for ; Thu, 7 Dec 2017 16:39:03 +0100 (CET) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id vB7Fd3gK013498; Thu, 7 Dec 2017 09:39:03 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1512661143; bh=fvDpfabkw3bg5WuHcjdC+ZFnNl6zs68V04j4iwARj5U=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bx6UqddXqiCq30WLxnKSzpz0Gnluz0nGkvLOQiN152Kzx4DnX3NauMHzzFjAx9A/4 I37Z2Qav7H4TSiiny27hgPoCqrvf/iVgeUEnbk91DMYNYA1RWh0BsjVseve6UecbLB skBwYuUzvQm75j56V6d34tsnzNKIIsY8pLbCTmWs= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id vB7Fd2Fk002073; Thu, 7 Dec 2017 09:39:02 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 7 Dec 2017 09:39:02 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 7 Dec 2017 09:39:02 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vB7Fd2lY029987; Thu, 7 Dec 2017 09:39:02 -0600 Received: from localhost (uda0226330.dhcp.ti.com [128.247.58.246]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id vB7Fd2329028; Thu, 7 Dec 2017 09:39:02 -0600 (CST) From: "Andrew F. Davis" To: Liam Girdwood , Mark Brown Date: Thu, 7 Dec 2017 09:38:58 -0600 Message-ID: <20171207153900.9831-9-afd@ti.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171207153900.9831-1-afd@ti.com> References: <20171207153900.9831-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, "Andrew F . Davis" Subject: [alsa-devel] [PATCH v3 08/10] ASoC: tlv320aic31xx: Add overflow detection support X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP Similar to short circuit detection, when the ADC/DAC is saturated and overflows poor audio quality can result and should be reported to the user. This device support Automatic Dynamic Range Compression (DRC) to reduce this but it is not enabled currently in this driver. Signed-off-by: Andrew F. Davis --- sound/soc/codecs/tlv320aic31xx.c | 20 +++++++++++++++++++- sound/soc/codecs/tlv320aic31xx.h | 7 +++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/tlv320aic31xx.c b/sound/soc/codecs/tlv320aic31xx.c index 500284853a5c..8ee407eab81b 100644 --- a/sound/soc/codecs/tlv320aic31xx.c +++ b/sound/soc/codecs/tlv320aic31xx.c @@ -1272,6 +1272,23 @@ static irqreturn_t aic31xx_irq(int irq, void *data) if (value & AIC31XX_HPRSCDETECT) dev_err(dev, "Short circuit on Right output is detected\n"); + ret = regmap_read(aic31xx->regmap, AIC31XX_OFFLAG, &value); + if (ret) { + dev_err(dev, "Failed to read overflow flag: %d\n", ret); + return IRQ_NONE; + } + + if (value & AIC31XX_DAC_OF_LEFT) + dev_err(dev, "Left-channel DAC overflow has occurred\n"); + if (value & AIC31XX_DAC_OF_RIGHT) + dev_err(dev, "Right-channel DAC overflow has occurred\n"); + if (value & AIC31XX_DAC_OF_SHIFTER) + dev_err(dev, "DAC barrel shifter overflow has occurred\n"); + if (value & AIC31XX_ADC_OF) + dev_err(dev, "ADC overflow has occurred\n"); + if (value & AIC31XX_ADC_OF_SHIFTER) + dev_err(dev, "ADC barrel shifter overflow has occurred\n"); + return IRQ_HANDLED; } @@ -1343,7 +1360,8 @@ static int aic31xx_i2c_probe(struct i2c_client *i2c, AIC31XX_GPIO1_FUNC_SHIFT); regmap_write(aic31xx->regmap, AIC31XX_INT1CTRL, - AIC31XX_SC); + AIC31XX_SC | + AIC31XX_ENGINE); ret = devm_request_threaded_irq(aic31xx->dev, aic31xx->irq, NULL, aic31xx_irq, diff --git a/sound/soc/codecs/tlv320aic31xx.h b/sound/soc/codecs/tlv320aic31xx.h index 9dc85b6f6ad3..d062663f66b5 100644 --- a/sound/soc/codecs/tlv320aic31xx.h +++ b/sound/soc/codecs/tlv320aic31xx.h @@ -166,6 +166,13 @@ enum aic31xx_type { #define AIC31XX_HPRDRVPWRSTATUS_MASK BIT(1) #define AIC31XX_SPRDRVPWRSTATUS_MASK BIT(0) +/* AIC31XX_OFFLAG */ +#define AIC31XX_DAC_OF_LEFT BIT(7) +#define AIC31XX_DAC_OF_RIGHT BIT(6) +#define AIC31XX_DAC_OF_SHIFTER BIT(5) +#define AIC31XX_ADC_OF BIT(3) +#define AIC31XX_ADC_OF_SHIFTER BIT(1) + /* AIC31XX_INTRDACFLAG */ #define AIC31XX_HPLSCDETECT BIT(7) #define AIC31XX_HPRSCDETECT BIT(6)