From patchwork Sun Feb 25 10:47:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans de Goede X-Patchwork-Id: 10240769 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E3FA460211 for ; Sun, 25 Feb 2018 10:51:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DAA2B29C07 for ; Sun, 25 Feb 2018 10:51:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CF43B29CCE; Sun, 25 Feb 2018 10:51:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0155B29C07 for ; Sun, 25 Feb 2018 10:51:29 +0000 (UTC) Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 06FE82679A8; Sun, 25 Feb 2018 11:48:16 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 7DC0A2674F2; Sun, 25 Feb 2018 11:47:56 +0100 (CET) Received: from mx1.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by alsa0.perex.cz (Postfix) with ESMTP id 1ADCB2674D2 for ; Sun, 25 Feb 2018 11:47:53 +0100 (CET) Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 830C440FB657; Sun, 25 Feb 2018 10:47:52 +0000 (UTC) Received: from shalem.localdomain.com (ovpn-116-99.ams2.redhat.com [10.36.116.99]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6441310B0F25; Sun, 25 Feb 2018 10:47:51 +0000 (UTC) From: Hans de Goede To: Mark Brown , Bard Liao , Oder Chiou , Pierre-Louis Bossart Date: Sun, 25 Feb 2018 11:47:06 +0100 Message-Id: <20180225104713.4745-26-hdegoede@redhat.com> In-Reply-To: <20180225104713.4745-1-hdegoede@redhat.com> References: <20180225104713.4745-1-hdegoede@redhat.com> X-Scanned-By: MIMEDefang 2.78 on 10.11.54.3 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Sun, 25 Feb 2018 10:47:52 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.11.55.7]); Sun, 25 Feb 2018 10:47:52 +0000 (UTC) for IP:'10.11.54.3' DOMAIN:'int-mx03.intmail.prod.int.rdu2.redhat.com' HELO:'smtp.corp.redhat.com' FROM:'hdegoede@redhat.com' RCPT:'' Cc: Hans de Goede , alsa-devel@alsa-project.org, Carlo Caione , Takashi Iwai Subject: [alsa-devel] [PATCH v2 25/32] ASoC: Intel: bytcr_rt5651: Configure PLL1 before using it X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP When platform_clock_control() first selects PLL1 as sysclk the PLL_CTRL registers have not been setup yet and we effectively have an invalid clock configuration until byt_rt5651_aif1_hw_params() gets called. Add a new byt_rt5651_prepare_and_enable_pll1() helper and use that from both platform_clock_control() and byt_rt5651_aif1_hw_params() to fix this. Tested-by: Carlo Caione Signed-off-by: Hans de Goede --- Changes in v2: -Make bclk_ratio configurable instead of hardcoding it to 50, this will be used when adding SSP0 support --- sound/soc/intel/boards/bytcr_rt5651.c | 73 +++++++++++++++++------------------ 1 file changed, 35 insertions(+), 38 deletions(-) diff --git a/sound/soc/intel/boards/bytcr_rt5651.c b/sound/soc/intel/boards/bytcr_rt5651.c index e44851448118..28219945912a 100644 --- a/sound/soc/intel/boards/bytcr_rt5651.c +++ b/sound/soc/intel/boards/bytcr_rt5651.c @@ -110,6 +110,38 @@ static void log_quirks(struct device *dev) #define BYT_CODEC_DAI1 "rt5651-aif1" +static int byt_rt5651_prepare_and_enable_pll1(struct snd_soc_dai *codec_dai, + int rate, int bclk_ratio) +{ + int clk_id, clk_freq, ret; + + /* Configure the PLL before selecting it */ + if (!(byt_rt5651_quirk & BYT_RT5651_MCLK_EN)) { + clk_id = RT5651_PLL1_S_BCLK1, + clk_freq = rate * bclk_ratio; + } else { + clk_id = RT5651_PLL1_S_MCLK; + if (byt_rt5651_quirk & BYT_RT5651_MCLK_25MHZ) + clk_freq = 25000000; + else + clk_freq = 19200000; + } + ret = snd_soc_dai_set_pll(codec_dai, 0, clk_id, clk_freq, rate * 512); + if (ret < 0) { + dev_err(codec_dai->codec->dev, "can't set pll: %d\n", ret); + return ret; + } + + ret = snd_soc_dai_set_sysclk(codec_dai, RT5651_SCLK_S_PLL1, + rate * 512, SND_SOC_CLOCK_IN); + if (ret < 0) { + dev_err(codec_dai->codec->dev, "can't set clock %d\n", ret); + return ret; + } + + return 0; +} + static int platform_clock_control(struct snd_soc_dapm_widget *w, struct snd_kcontrol *k, int event) { @@ -135,9 +167,7 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w, return ret; } } - ret = snd_soc_dai_set_sysclk(codec_dai, RT5651_SCLK_S_PLL1, - 48000 * 512, - SND_SOC_CLOCK_IN); + ret = byt_rt5651_prepare_and_enable_pll1(codec_dai, 48000, 50); } else { /* * Set codec clock source to internal clock before @@ -251,44 +281,11 @@ static int byt_rt5651_aif1_hw_params(struct snd_pcm_substream *substream, { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; - int ret; + int rate = params_rate(params); snd_soc_dai_set_bclk_ratio(codec_dai, 50); - ret = snd_soc_dai_set_sysclk(codec_dai, RT5651_SCLK_S_PLL1, - params_rate(params) * 512, - SND_SOC_CLOCK_IN); - if (ret < 0) { - dev_err(rtd->dev, "can't set codec clock %d\n", ret); - return ret; - } - - if (!(byt_rt5651_quirk & BYT_RT5651_MCLK_EN)) { - /* 2x25 bit slots on SSP2 */ - ret = snd_soc_dai_set_pll(codec_dai, 0, - RT5651_PLL1_S_BCLK1, - params_rate(params) * 50, - params_rate(params) * 512); - } else { - if (byt_rt5651_quirk & BYT_RT5651_MCLK_25MHZ) { - ret = snd_soc_dai_set_pll(codec_dai, 0, - RT5651_PLL1_S_MCLK, - 25000000, - params_rate(params) * 512); - } else { - ret = snd_soc_dai_set_pll(codec_dai, 0, - RT5651_PLL1_S_MCLK, - 19200000, - params_rate(params) * 512); - } - } - - if (ret < 0) { - dev_err(rtd->dev, "can't set codec pll: %d\n", ret); - return ret; - } - - return 0; + return byt_rt5651_prepare_and_enable_pll1(codec_dai, rate, 50); } static int byt_rt5651_quirk_cb(const struct dmi_system_id *id)