From patchwork Fri Apr 27 08:17:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 10367665 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E5EB4601D3 for ; Fri, 27 Apr 2018 08:17:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D92AE29322 for ; Fri, 27 Apr 2018 08:17:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CC91B29325; Fri, 27 Apr 2018 08:17:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 19FBA29322 for ; Fri, 27 Apr 2018 08:17:05 +0000 (UTC) Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 1D2702678A0; Fri, 27 Apr 2018 10:16:56 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id A6706267872; Fri, 27 Apr 2018 10:16:52 +0200 (CEST) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by alsa0.perex.cz (Postfix) with ESMTP id BB0BD267230 for ; Fri, 27 Apr 2018 10:16:50 +0200 (CEST) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w3R8Gn9l024511; Fri, 27 Apr 2018 03:16:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1524817009; bh=WSc9or1bp4qGUTUn1yY/fjkanyNg8mhA+l9vbC/n7ro=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Svc5MTUPlJY4JLdZ8jt/GgmeM3idT1UiPVE7niCTyZRMdsXk9Iszx4ScsoF0WHjVS g3Vn90KfkU/BiYGluTNb8UTui7YX2i/adeiFtwPmXWUWYMU5yPS4qHNy1YtGdFygzs oggYxDifn3k39Xk1V+I9jAQv9dQd2eE4TqpjDF1Y= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3R8GnDi002014; Fri, 27 Apr 2018 03:16:49 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 27 Apr 2018 03:16:49 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 27 Apr 2018 03:16:49 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w3R8GgBr012074; Fri, 27 Apr 2018 03:16:47 -0500 From: Peter Ujfalusi To: Mark Brown , Liam Girdwood , , Date: Fri, 27 Apr 2018 11:17:11 +0300 Message-ID: <20180427081715.28791-3-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180427081715.28791-1-peter.ujfalusi@ti.com> References: <20180427081715.28791-1-peter.ujfalusi@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: alsa-devel@alsa-project.org, linux-omap@vger.kernel.org, aaro.koskinen@iki.fi Subject: [alsa-devel] [PATCH v2 2/6] ARM: dts: omap2420-n810: Correct the audio codec (tlv320aic33) node X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP - The n810 uses tlv320aic33 codec. - GPIO118 is used as reset GPIO for the codec, which was missing. - The MCLK of the codec is connected to the SYS_CLKOUT2 of omap2420. The SYS_CLKOUT2 needs to be running at 12MHz. - Add the pinctrl entries to configure the pins for GPIO118 and SYS_CLKOUT2 - Set DMIC clk mode for GPIO1 - Set DMIC data in for GPIO2 - Select 2V for the DMIC bias - Add fixed regulators for the codec Signed-off-by: Peter Ujfalusi --- arch/arm/boot/dts/omap2420-n810.dts | 46 +++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap2420-n810.dts b/arch/arm/boot/dts/omap2420-n810.dts index 4c412a480c3e..96b9913ecc1f 100644 --- a/arch/arm/boot/dts/omap2420-n810.dts +++ b/arch/arm/boot/dts/omap2420-n810.dts @@ -6,6 +6,20 @@ / { model = "Nokia N810"; compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2"; + + vio_ape: vio_ape { + compatible = "regulator-fixed"; + regulator-name = "vio_ape"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + v28_aic: v28_aic { + compatible = "regulator-fixed"; + regulator-name = "v28_aic"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; }; &omap2420_pmx { @@ -17,14 +31,42 @@ OMAP2420_CORE_IOPAD(0x0127, PIN_OUTPUT | MUX_MODE1) /* eac_ac_dout.mcbsp2_dx */ >; }; + + aic33_pins: aic33_pins { + pinctrl-single,pins = < + OMAP2420_CORE_IOPAD(0x0129, PIN_OUTPUT | MUX_MODE3) /* eac_ac_rst.gpio118 */ + OMAP2420_CORE_IOPAD(0x00e8, PIN_OUTPUT | MUX_MODE2) /* vlynq_tx1.sys_clkout2 */ + >; + }; }; &i2c2 { - aic3x@18 { - compatible = "tlv320aic3x"; + aic33@18 { + compatible = "ti,tlv320aic33"; reg = <0x18>; + + pinctrl-names = "default"; + pinctrl-0 = <&aic33_pins>; + + gpio-reset = <&gpio4 22 GPIO_ACTIVE_LOW>; /* gpio118 */ + + ai3x-gpio-func = < + 10 /* AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK */ + 5 /* AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT */ + >; + ai3x-micbias-vg = <1>; /* 2V */ + + AVDD-supply = <&v28_aic>; + DRVDD-supply = <&v28_aic>; + IOVDD-supply = <&vio_ape>; + DVDD-supply = <&vio_ape>; + + assigned-clocks = <&sys_clkout2_src>, <&sys_clkout2>; + assigned-clock-parents = <&func_96m_ck>; + assigned-clock-rates = <0>, <12000000>; }; }; + &mcbsp2 { pinctrl-names = "default"; pinctrl-0 = <&mcbsp2_pins>;