@@ -105,5 +105,7 @@ const struct sof_intel_dsp_desc apl_chip_info = {
.ipc_ack_mask = HDA_DSP_REG_HIPCIE_DONE,
.ipc_ctl = HDA_DSP_REG_HIPCCTL,
.rom_init_timeout = 150,
+ .ssp_count = APL_SSP_COUNT,
+ .ssp_base_offset = APL_SSP_BASE_OFFSET,
};
EXPORT_SYMBOL(apl_chip_info);
@@ -246,5 +246,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
.ipc_ctl = CNL_DSP_REG_HIPCCTL,
.rom_init_timeout = 300,
+ .ssp_count = CNL_SSP_COUNT,
+ .ssp_base_offset = CNL_SSP_BASE_OFFSET,
};
EXPORT_SYMBOL(cnl_chip_info);
@@ -345,6 +345,10 @@
/* Host Device Memory Size of a Single SSP */
#define SSP_DEV_MEM_SIZE 0x1000
+/* SSP Count of the Platform */
+#define APL_SSP_COUNT 6
+#define CNL_SSP_COUNT 3
+
#define HDA_IDISP_CODEC(x) ((x) & BIT(2))
struct sof_intel_dsp_bdl {
@@ -162,6 +162,8 @@ struct sof_intel_dsp_desc {
int ipc_ack_mask;
int ipc_ctl;
int rom_init_timeout;
+ int ssp_count; /* ssp count of the platform */
+ int ssp_base_offset; /* base address of the SSPs */
};
extern const struct snd_sof_dsp_ops sof_tng_ops;