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[86.30.250.44]) by smtp.gmail.com with ESMTPSA id d10sm2035308wrh.91.2019.06.07.01.57.12 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 07 Jun 2019 01:57:12 -0700 (PDT) From: Srinivas Kandagatla To: broonie@kernel.org, vkoul@kernel.org Date: Fri, 7 Jun 2019 09:56:42 +0100 Message-Id: <20190607085643.932-6-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190607085643.932-1-srinivas.kandagatla@linaro.org> References: <20190607085643.932-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, alsa-devel@alsa-project.org, pierre-louis.bossart@linux.intel.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, Srinivas Kandagatla Subject: [alsa-devel] [RFC PATCH 5/6] dt-bindings: soundwire: add bindings for Qcom controller X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds bindings for Qualcomm soundwire controller. Qualcomm SoundWire Master controller is present in most Qualcomm SoCs either integrated as part of WCD audio codecs via slimbus or as part of SOC I/O. Signed-off-by: Srinivas Kandagatla --- .../bindings/soundwire/qcom,swr.txt | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/soundwire/qcom,swr.txt diff --git a/Documentation/devicetree/bindings/soundwire/qcom,swr.txt b/Documentation/devicetree/bindings/soundwire/qcom,swr.txt new file mode 100644 index 000000000000..eb84d0f4f36f --- /dev/null +++ b/Documentation/devicetree/bindings/soundwire/qcom,swr.txt @@ -0,0 +1,62 @@ +Qualcomm SoundWire Controller + +This binding describes the Qualcomm SoundWire Controller Bindings. + +Required properties: + +- compatible: Must be "qcom,soundwire-v..", + example: + "qcom,soundwire-v1.3.0" + "qcom,soundwire-v1.5.0" + "qcom,soundwire-v1.6.0" +- reg: SoundWire controller address space. +- interrupts: SoundWire controller interrupt. +- clock-names: Must contain "iface". +- clocks: Interface clocks needed for controller. +- #sound-dai-cells: Must be 1 for digital audio interfaces on the controllers. +- #address-cells: Must be 1 for SoundWire devices; +- #size-cells: Must be <0> as SoundWire addresses have no size component. +- qcom,dout-ports: Must be count of data out ports +- qcom,din-ports: Must be count of data in ports +- qcom,ports-offset1: Must be frame offset1 of each data port. + Out followed by In. Used for Block size calculation. +- qcom,ports-offset2: Must be frame offset2 of each data port. + Out followed by In. Used for Block size calculation. +- qcom,ports-sinterval-low: Must be sample interval low of each data port. + Out followed by In. Used for Sample Interval calculation. + += SoundWire devices +Each subnode of the bus represents SoundWire device attached to it. +The properties of these nodes are defined by the individual bindings. + += EXAMPLE +The following example represents a SoundWire controller on DB845c board +which has controller integrated inside WCD934x codec on SDM845 SoC. + +soundwire: soundwire@c85 { + compatible = "qcom,soundwire-v1.3.0"; + reg = <0xc85 0x20>; + interrupts = <20 IRQ_TYPE_EDGE_RISING>; + clocks = <&wcc>; + clock-names = "iface"; + #sound-dai-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + qcom,dout-ports = <6>; + qcom,din-ports = <2>; + qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; + + /* Left Speaker */ + wsa8810@1{ + .... + reg = <1>; + }; + + /* Right Speaker */ + wsa8810@2{ + .... + reg = <2>; + }; +};