@@ -323,12 +323,11 @@ int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
enum sof_d0_substate d0_substate)
{
struct hdac_bus *bus = sof_to_bus(sdev);
- int retry = 50;
int ret;
u8 value;
/* Write to D0I3C after Command-In-Progress bit is cleared */
- ret = hda_dsp_wait_d0i3c_done(sdev, retry);
+ ret = hda_dsp_wait_d0i3c_done(sdev, HDA_DSP_REG_POLL_RETRY_COUNT);
if (ret < 0) {
dev_err(bus->dev, "CIP timeout before D0I3C update!\n");
return ret;
@@ -339,8 +338,7 @@ int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);
/* Wait for cmd in progress to be cleared before exiting the function */
- retry = 50;
- ret = hda_dsp_wait_d0i3c_done(sdev, retry);
+ ret = hda_dsp_wait_d0i3c_done(sdev, HDA_DSP_REG_POLL_RETRY_COUNT);
if (ret < 0) {
dev_err(bus->dev, "CIP timeout after D0I3C update!\n");
return ret;
@@ -214,6 +214,7 @@
#define HDA_DSP_CTRL_RESET_TIMEOUT 100
#define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
#define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */
+#define HDA_DSP_REG_POLL_RETRY_COUNT 50
#define HDA_DSP_ADSPIC_IPC 1
#define HDA_DSP_ADSPIS_IPC 1