diff mbox series

[4/6] soundwire: qcom: start the clock during initialization

Message ID 20210129173248.5941-5-srinivas.kandagatla@linaro.org (mailing list archive)
State New, archived
Headers show
Series soundwire: qcom: various improvements | expand

Commit Message

Srinivas Kandagatla Jan. 29, 2021, 5:32 p.m. UTC
Start the clock during initialization.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 drivers/soundwire/qcom.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Vinod Koul Feb. 1, 2021, 2:21 p.m. UTC | #1
On 29-01-21, 17:32, Srinivas Kandagatla wrote:
> Start the clock during initialization.

A detailed log please, which clock..? Also how do older controllers work
w/o this clk

> 
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> ---
>  drivers/soundwire/qcom.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
> index 3669bac11a32..83df15d83935 100644
> --- a/drivers/soundwire/qcom.c
> +++ b/drivers/soundwire/qcom.c
> @@ -47,6 +47,8 @@
>  #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)		(0x101C + 0x40 * (m))
>  #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK			GENMASK(2, 0)
>  #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK			GENMASK(7, 3)
> +#define SWRM_MCP_BUS_CTRL					0x1044
> +#define SWRM_MCP_BUS_CLK_START					BIT(1)
>  #define SWRM_MCP_CFG_ADDR					0x1048
>  #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK		GENMASK(21, 17)
>  #define SWRM_DEF_CMD_NO_PINGS					0x1f
> @@ -345,6 +347,7 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
>  	u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
>  	ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
>  
> +	ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
>  	/* Configure number of retries of a read/write cmd */
>  	if (ctrl->version_major == 1 && ctrl->version_minor >= 5 &&
>  	    ctrl->version_step >= 1) {
> -- 
> 2.21.0
Srinivas Kandagatla Feb. 1, 2021, 3:50 p.m. UTC | #2
On 01/02/2021 14:21, Vinod Koul wrote:
> On 29-01-21, 17:32, Srinivas Kandagatla wrote:
>> Start the clock during initialization.
> 
> A detailed log please, which clock..? Also how do older controllers work
> w/o this clk

By default this is ON, however depending on that is not really reliable!

Explicitly enabling this will make things clear when we add clk pause 
feature for this driver!

--srini
> 
>>
>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
>> ---
>>   drivers/soundwire/qcom.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
>> index 3669bac11a32..83df15d83935 100644
>> --- a/drivers/soundwire/qcom.c
>> +++ b/drivers/soundwire/qcom.c
>> @@ -47,6 +47,8 @@
>>   #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)		(0x101C + 0x40 * (m))
>>   #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK			GENMASK(2, 0)
>>   #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK			GENMASK(7, 3)
>> +#define SWRM_MCP_BUS_CTRL					0x1044
>> +#define SWRM_MCP_BUS_CLK_START					BIT(1)
>>   #define SWRM_MCP_CFG_ADDR					0x1048
>>   #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK		GENMASK(21, 17)
>>   #define SWRM_DEF_CMD_NO_PINGS					0x1f
>> @@ -345,6 +347,7 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
>>   	u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
>>   	ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
>>   
>> +	ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
>>   	/* Configure number of retries of a read/write cmd */
>>   	if (ctrl->version_major == 1 && ctrl->version_minor >= 5 &&
>>   	    ctrl->version_step >= 1) {
>> -- 
>> 2.21.0
>
Vinod Koul Feb. 2, 2021, 4:46 a.m. UTC | #3
On 01-02-21, 15:50, Srinivas Kandagatla wrote:
> 
> 
> On 01/02/2021 14:21, Vinod Koul wrote:
> > On 29-01-21, 17:32, Srinivas Kandagatla wrote:
> > > Start the clock during initialization.
> > 
> > A detailed log please, which clock..? Also how do older controllers work
> > w/o this clk
> 
> By default this is ON, however depending on that is not really reliable!
> 
> Explicitly enabling this will make things clear when we add clk pause
> feature for this driver!

lets add this in the log please
diff mbox series

Patch

diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
index 3669bac11a32..83df15d83935 100644
--- a/drivers/soundwire/qcom.c
+++ b/drivers/soundwire/qcom.c
@@ -47,6 +47,8 @@ 
 #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m)		(0x101C + 0x40 * (m))
 #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK			GENMASK(2, 0)
 #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK			GENMASK(7, 3)
+#define SWRM_MCP_BUS_CTRL					0x1044
+#define SWRM_MCP_BUS_CLK_START					BIT(1)
 #define SWRM_MCP_CFG_ADDR					0x1048
 #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK		GENMASK(21, 17)
 #define SWRM_DEF_CMD_NO_PINGS					0x1f
@@ -345,6 +347,7 @@  static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
 	u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
 	ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
 
+	ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
 	/* Configure number of retries of a read/write cmd */
 	if (ctrl->version_major == 1 && ctrl->version_minor >= 5 &&
 	    ctrl->version_step >= 1) {