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[82.65.169.74]) by smtp.googlemail.com with ESMTPSA id n2sm3151431edi.32.2021.04.21.05.05.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Apr 2021 05:05:38 -0700 (PDT) From: Jerome Brunet To: Mark Brown Subject: [PATCH v2 3/5] ASoC: rt5682: clock driver must use the clock provider API Date: Wed, 21 Apr 2021 14:05:10 +0200 Message-Id: <20210421120512.413057-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210421120512.413057-1-jbrunet@baylibre.com> References: <20210421120512.413057-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-Patchwork-Bot: notify Cc: Stephen Boyd , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Jerome Brunet X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Clock drivers ops should not call the clk API but the clock provider (clk_hw) instead. Signed-off-by: Jerome Brunet --- sound/soc/codecs/rt5682.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sound/soc/codecs/rt5682.c b/sound/soc/codecs/rt5682.c index a5aacfe01a0d..e4c91571abae 100644 --- a/sound/soc/codecs/rt5682.c +++ b/sound/soc/codecs/rt5682.c @@ -2634,7 +2634,7 @@ static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate, container_of(hw, struct rt5682_priv, dai_clks_hw[RT5682_DAI_WCLK_IDX]); struct snd_soc_component *component = rt5682->component; - struct clk *parent_clk; + struct clk_hw *parent_hw; const char * const clk_name = clk_hw_get_name(hw); int pre_div; unsigned int clk_pll2_out; @@ -2649,8 +2649,8 @@ static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate, * * It will set the codec anyway by assuming mclk is 48MHz. */ - parent_clk = clk_get_parent(hw->clk); - if (!parent_clk) + parent_hw = clk_hw_get_parent(hw); + if (!parent_hw) dev_warn(component->dev, "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n", CLK_PLL2_FIN);