diff mbox series

[7/7] ASoC: fsl_sai: implement 1:1 bclk:mclk ratio support

Message ID 20220303073028.594183-8-s.hauer@pengutronix.de (mailing list archive)
State Accepted
Commit a50b7926d015c3b8194ab1d7c8aa86db8e4b7700
Headers show
Series ASoC: fsl_sai: Cleanups and 1:1 bclk:mclk ratio support | expand

Commit Message

Sascha Hauer March 3, 2022, 7:30 a.m. UTC 
From: Ahmad Fatoum <a.fatoum@pengutronix.de>

With higher channel counts, we may need higher clock rates.  Starting
with SAI v3.1 (i.MX8MM), we can bypass the divider and get a 1:1
bclk:mclk ratio. Add the necessary support.

Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 sound/soc/fsl/fsl_sai.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 818bb982427f8..0845f50735248 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -347,6 +347,7 @@  static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
 	int adir = tx ? RX : TX;
 	int dir = tx ? TX : RX;
 	u32 id;
+	bool support_1_1_ratio = sai->verid.version >= 0x0301;
 
 	/* Don't apply to consumer mode */
 	if (sai->is_consumer_mode)
@@ -367,7 +368,11 @@  static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
 			continue;
 
 		ratio = DIV_ROUND_CLOSEST(clk_rate, freq);
-		if (!ratio || ratio > 512 || ratio & 1)
+		if (!ratio || ratio > 512)
+			continue;
+		if (ratio == 1 && !support_1_1_ratio)
+			continue;
+		else if (ratio & 1)
 			continue;
 
 		diff = abs((long)clk_rate - ratio * freq);
@@ -422,7 +427,15 @@  static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
 
 	regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK,
 			   FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
-	regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_DIV_MASK, savediv / 2 - 1);
+
+	if (savediv == 1)
+		regmap_update_bits(sai->regmap, reg,
+				   FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
+				   FSL_SAI_CR2_BYP);
+	else
+		regmap_update_bits(sai->regmap, reg,
+				   FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP,
+				   savediv / 2 - 1);
 
 	return 0;
 }