From patchwork Wed Jun 22 07:46:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vitaly Rodionov X-Patchwork-Id: 12890281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 291F9C433EF for ; Wed, 22 Jun 2022 07:50:54 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 600B61FFE; Wed, 22 Jun 2022 09:50:02 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 600B61FFE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1655884252; bh=4osVN2gxBC3rbdED3ZmBiVIVKBbUlu8oCWkt4+YNe6o=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=qQXcggFlcJ5wTw8/Vm5AFY8RbiM4ik2zypwSMPZDjVMeQ0c0Y/1KkfsVVVn30nMVD Oa7oyNL8c/3NCgJuOWiWLveuJtGr1r/4Ez9lJYJxnJd+ThjEnWQPylwPvXSzNPbYR7 egHwiN+PvMzxY06R3vGYkuRYSWYW4lOl0la5h9ek= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 14D0BF80589; Wed, 22 Jun 2022 09:47:28 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 14166F80558; Wed, 22 Jun 2022 09:47:18 +0200 (CEST) Received: from mx0b-001ae601.pphosted.com (mx0b-001ae601.pphosted.com [67.231.152.168]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 7CF83F80535 for ; Wed, 22 Jun 2022 09:47:03 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 7CF83F80535 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=cirrus.com header.i=@cirrus.com header.b="NrEYe35O" Received: from pps.filterd (m0077474.ppops.net [127.0.0.1]) by mx0b-001ae601.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 25M7Su1O003738; Wed, 22 Jun 2022 02:47:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=yEUjvzIDkSuesN4ILaRzVOzgfN/9xKEkJ3H0pI1QULM=; b=NrEYe35OCbFA5K4w3y/h6iCQ33rEWbfuNmpShF8nhhQGgg0RlCVdt9Tn+Bve2J26mLLF GENfcg63ZJ4IBPiv0aBBEZrX3fAiQXNpHFtpszx49M9RG52ASoNkkwFWRTHbmlX9VrIx t2cPHlIpZByDXPm9qMapNjd8GVMXBRrTT2atCtkyj0Dbgk4zn1gAnCMxrseOn6gbAG/t iguSEcUEsF4wsoSRezBFIXz6HhcCR/K5FIq5Qdl7wDONSEwyN2hx5tLKffLE6hXgz1YI zlMhHnO4ZcRnJkTUan4aCIlhyBAaRXJyoBIpPQPaV75fsfDW9qr6bm/HLYtVWKtPiCpl ZA== Received: from ediex02.ad.cirrus.com ([84.19.233.68]) by mx0b-001ae601.pphosted.com (PPS) with ESMTPS id 3gsb4p4mwq-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Wed, 22 Jun 2022 02:47:01 -0500 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 22 Jun 2022 08:46:59 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Wed, 22 Jun 2022 08:46:59 +0100 Received: from vitaly-Legion-7-16ACHg6.ad.cirrus.com (unknown [198.90.238.175]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 89FD47C; Wed, 22 Jun 2022 07:46:59 +0000 (UTC) From: Vitaly Rodionov To: Jaroslav Kysela , Takashi Iwai , Mark Brown Subject: [PATCH v7 12/14] ALSA: hda: cs35l41: Add defaulted values into dsp bypass config sequence Date: Wed, 22 Jun 2022 08:46:51 +0100 Message-ID: <20220622074653.179078-13-vitalyr@opensource.cirrus.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220622074653.179078-1-vitalyr@opensource.cirrus.com> References: <20220622074653.179078-1-vitalyr@opensource.cirrus.com> MIME-Version: 1.0 X-Proofpoint-GUID: GPYNT5VgfyCEfZnDm8cGUkg_0o_g_PpR X-Proofpoint-ORIG-GUID: GPYNT5VgfyCEfZnDm8cGUkg_0o_g_PpR X-Proofpoint-Spam-Reason: safe Cc: patches@opensource.cirrus.com, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Stefan Binding X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Stefan Binding The config sequences for running with and without firmware and DSP are different. The original behavior assumed that we would only run without DSP only in the case where firmware load failed. This meant the non-firmware sequence was written with the assumtion that various registers would be set to their default value. However, to support the ability to unload the firmware, the non-firmware register sequence must be updated to update all required registers, including values that would be defaulted, in case the firmware sequence, which could have already run, has changed their value. Signed-off-by: Stefan Binding Signed-off-by: Vitaly Rodionov --- sound/pci/hda/cs35l41_hda.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/sound/pci/hda/cs35l41_hda.c b/sound/pci/hda/cs35l41_hda.c index ef3dfda7b03e..e51cdf42d3dc 100644 --- a/sound/pci/hda/cs35l41_hda.c +++ b/sound/pci/hda/cs35l41_hda.c @@ -35,11 +35,24 @@ static const struct reg_sequence cs35l41_hda_config[] = { { CS35L41_PLL_CLK_CTRL, 0x00000430 }, // 3072000Hz, BCLK Input, PLL_REFCLK_EN = 1 + { CS35L41_DSP_CLK_CTRL, 0x00000003 }, // DSP CLK EN { CS35L41_GLOBAL_CLK_CTRL, 0x00000003 }, // GLOBAL_FS = 48 kHz { CS35L41_SP_ENABLES, 0x00010000 }, // ASP_RX1_EN = 1 { CS35L41_SP_RATE_CTRL, 0x00000021 }, // ASP_BCLK_FREQ = 3.072 MHz { CS35L41_SP_FORMAT, 0x20200200 }, // 32 bits RX/TX slots, I2S, clk consumer + { CS35L41_SP_HIZ_CTRL, 0x00000002 }, // Hi-Z unused + { CS35L41_SP_TX_WL, 0x00000018 }, // 24 cycles/slot + { CS35L41_SP_RX_WL, 0x00000018 }, // 24 cycles/slot { CS35L41_DAC_PCM1_SRC, 0x00000008 }, // DACPCM1_SRC = ASPRX1 + { CS35L41_ASP_TX1_SRC, 0x00000018 }, // ASPTX1 SRC = VMON + { CS35L41_ASP_TX2_SRC, 0x00000019 }, // ASPTX2 SRC = IMON + { CS35L41_ASP_TX3_SRC, 0x00000032 }, // ASPTX3 SRC = ERRVOL + { CS35L41_ASP_TX4_SRC, 0x00000033 }, // ASPTX4 SRC = CLASSH_TGT + { CS35L41_DSP1_RX1_SRC, 0x00000008 }, // DSP1RX1 SRC = ASPRX1 + { CS35L41_DSP1_RX2_SRC, 0x00000009 }, // DSP1RX2 SRC = ASPRX2 + { CS35L41_DSP1_RX3_SRC, 0x00000018 }, // DSP1RX3 SRC = VMON + { CS35L41_DSP1_RX4_SRC, 0x00000019 }, // DSP1RX4 SRC = IMON + { CS35L41_DSP1_RX5_SRC, 0x00000020 }, // DSP1RX5 SRC = ERRVOL { CS35L41_AMP_DIG_VOL_CTRL, 0x00000000 }, // AMP_VOL_PCM 0.0 dB { CS35L41_AMP_GAIN_CTRL, 0x00000084 }, // AMP_GAIN_PCM 4.5 dB };