| Message ID | 20221018-clk-range-checks-fixes-v2-35-f6736dec138e@cerno.tech (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: Make determine_rate mandatory for muxes | expand |
On Fri, Nov 4, 2022 at 2:32 PM Maxime Ripard <maxime@cerno.tech> wrote: > The UX500 sysctrl "set_parent" clocks implement a mux with a set_parent > hook, but doesn't provide a determine_rate implementation. > > This is a bit odd, since set_parent() is there to, as its name implies, > change the parent of a clock. However, the most likely candidate to > trigger that parent change is a call to clk_set_rate(), with > determine_rate() figuring out which parent is the best suited for a > given rate. > > The other trigger would be a call to clk_set_parent(), but it's far less > used, and it doesn't look like there's any obvious user for that clock. > > So, the set_parent hook is effectively unused, possibly because of an > oversight. However, it could also be an explicit decision by the > original author to avoid any reparenting but through an explicit call to > clk_set_parent(). > > The latter case would be equivalent to setting the flag > CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook > to __clk_mux_determine_rate(). Indeed, if no determine_rate > implementation is provided, clk_round_rate() (through > clk_core_round_rate_nolock()) will call itself on the parent if > CLK_SET_RATE_PARENT is set, and will not change the clock rate > otherwise. __clk_mux_determine_rate() has the exact same behavior when > CLK_SET_RATE_NO_REPARENT is set. > > And if it was an oversight, then we are at least explicit about our > behavior now and it can be further refined down the line. > > Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
On Fri, 4 Nov 2022 at 14:32, Maxime Ripard <maxime@cerno.tech> wrote: > > The UX500 sysctrl "set_parent" clocks implement a mux with a set_parent > hook, but doesn't provide a determine_rate implementation. > > This is a bit odd, since set_parent() is there to, as its name implies, > change the parent of a clock. However, the most likely candidate to > trigger that parent change is a call to clk_set_rate(), with > determine_rate() figuring out which parent is the best suited for a > given rate. > > The other trigger would be a call to clk_set_parent(), but it's far less > used, and it doesn't look like there's any obvious user for that clock. If I recall correctly, that is the use case we did target for these types of clocks. See sound/soc/ux500/ux500_ab85xx.c, for example. Maybe there are some additional pieces missing from the old down stream kernel, I don't have full picture, sorry. Anyway, if I am not wrong, this was about supporting a low-power audio use case, which requires us to switch the parent clock (to avoid wasting energy). > > So, the set_parent hook is effectively unused, possibly because of an > oversight. However, it could also be an explicit decision by the > original author to avoid any reparenting but through an explicit call to > clk_set_parent(). Yes, this was the reason. As a matter of fact, I don't even recall that re-parenting was possible through clk_set_rate() when this clock driver was introduced. But, I might be wrong, it's quite a while ago. > > The latter case would be equivalent to setting the flag > CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook > to __clk_mux_determine_rate(). Indeed, if no determine_rate > implementation is provided, clk_round_rate() (through > clk_core_round_rate_nolock()) will call itself on the parent if > CLK_SET_RATE_PARENT is set, and will not change the clock rate > otherwise. __clk_mux_determine_rate() has the exact same behavior when > CLK_SET_RATE_NO_REPARENT is set. > > And if it was an oversight, then we are at least explicit about our > behavior now and it can be further refined down the line. > > Signed-off-by: Maxime Ripard <maxime@cerno.tech> Seems reasonable to me! Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Kind regards Uffe > --- > drivers/clk/ux500/clk-sysctrl.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c > index 702f2f8b43fa..d36336665b6d 100644 > --- a/drivers/clk/ux500/clk-sysctrl.c > +++ b/drivers/clk/ux500/clk-sysctrl.c > @@ -110,6 +110,7 @@ static const struct clk_ops clk_sysctrl_gate_fixed_rate_ops = { > }; > > static const struct clk_ops clk_sysctrl_set_parent_ops = { > + .determine_rate = __clk_mux_determine_rate, > .set_parent = clk_sysctrl_set_parent, > .get_parent = clk_sysctrl_get_parent, > }; > @@ -220,6 +221,7 @@ struct clk *clk_reg_sysctrl_set_parent(struct device *dev, > unsigned long flags) > { > return clk_reg_sysctrl(dev, name, parent_names, num_parents, > - reg_sel, reg_mask, reg_bits, 0, 0, flags, > + reg_sel, reg_mask, reg_bits, 0, 0, > + flags | CLK_SET_RATE_NO_REPARENT, > &clk_sysctrl_set_parent_ops); > } > > -- > b4 0.11.0-dev-99e3a
On Thu, Nov 10, 2022 at 12:29 PM Ulf Hansson <ulf.hansson@linaro.org> wrote: > On Fri, 4 Nov 2022 at 14:32, Maxime Ripard <maxime@cerno.tech> wrote: > > > > The UX500 sysctrl "set_parent" clocks implement a mux with a set_parent > > hook, but doesn't provide a determine_rate implementation. > > > > This is a bit odd, since set_parent() is there to, as its name implies, > > change the parent of a clock. However, the most likely candidate to > > trigger that parent change is a call to clk_set_rate(), with > > determine_rate() figuring out which parent is the best suited for a > > given rate. > > > > The other trigger would be a call to clk_set_parent(), but it's far less > > used, and it doesn't look like there's any obvious user for that clock. > > If I recall correctly, that is the use case we did target for these > types of clocks. See sound/soc/ux500/ux500_ab85xx.c, for example. Hm I am trying to get that driver to work ... from time to time. It's just that ALSA SoC DT has changed to much that it turns out into a complete rewrite :/ So in sound/soc/ux500/mop500_ab8500.c I see this: status = clk_set_parent(drvdata->clk_ptr_intclk, clk_ptr); if (status) (...) and there is elaborate code to switch between "SYSCLK" and "ULPCLK" (ulta-low power clock). Just like you say... however a clock named SYSCLK or ULPCLK does not appear in the code in drivers/clk/ux500 or any DT bindings so... it seems to be non-working for the time being. Yours, Linus Walleij
On Thu, 10 Nov 2022 at 12:39, Linus Walleij <linus.walleij@linaro.org> wrote: > > On Thu, Nov 10, 2022 at 12:29 PM Ulf Hansson <ulf.hansson@linaro.org> wrote: > > On Fri, 4 Nov 2022 at 14:32, Maxime Ripard <maxime@cerno.tech> wrote: > > > > > > The UX500 sysctrl "set_parent" clocks implement a mux with a set_parent > > > hook, but doesn't provide a determine_rate implementation. > > > > > > This is a bit odd, since set_parent() is there to, as its name implies, > > > change the parent of a clock. However, the most likely candidate to > > > trigger that parent change is a call to clk_set_rate(), with > > > determine_rate() figuring out which parent is the best suited for a > > > given rate. > > > > > > The other trigger would be a call to clk_set_parent(), but it's far less > > > used, and it doesn't look like there's any obvious user for that clock. > > > > If I recall correctly, that is the use case we did target for these > > types of clocks. See sound/soc/ux500/ux500_ab85xx.c, for example. > > Hm I am trying to get that driver to work ... from time to time. > It's just that ALSA SoC DT has changed to much that it turns out > into a complete rewrite :/ > > So in sound/soc/ux500/mop500_ab8500.c > I see this: > > status = clk_set_parent(drvdata->clk_ptr_intclk, clk_ptr); > if (status) > (...) > > and there is elaborate code to switch between "SYSCLK" and > "ULPCLK" (ulta-low power clock). Just like you say... however > a clock named SYSCLK or ULPCLK does not appear in the > code in drivers/clk/ux500 or any DT bindings so... it seems to > be non-working for the time being. It's definitely not working, but the corresponding clocks ("ulpclk", "intclk", "audioclk", etc) are being registered in ab8500_reg_clks(). What seems to be missing is a DT conversion for these clocks, so they can be consumed properly. Right? Kind regards Uffe
On Thu, Nov 10, 2022 at 2:05 PM Ulf Hansson <ulf.hansson@linaro.org> wrote: > On Thu, 10 Nov 2022 at 12:39, Linus Walleij <linus.walleij@linaro.org> wrote: > > > > On Thu, Nov 10, 2022 at 12:29 PM Ulf Hansson <ulf.hansson@linaro.org> wrote: > > > On Fri, 4 Nov 2022 at 14:32, Maxime Ripard <maxime@cerno.tech> wrote: > > > > > > > > The UX500 sysctrl "set_parent" clocks implement a mux with a set_parent > > > > hook, but doesn't provide a determine_rate implementation. > > > > > > > > This is a bit odd, since set_parent() is there to, as its name implies, > > > > change the parent of a clock. However, the most likely candidate to > > > > trigger that parent change is a call to clk_set_rate(), with > > > > determine_rate() figuring out which parent is the best suited for a > > > > given rate. > > > > > > > > The other trigger would be a call to clk_set_parent(), but it's far less > > > > used, and it doesn't look like there's any obvious user for that clock. > > > > > > If I recall correctly, that is the use case we did target for these > > > types of clocks. See sound/soc/ux500/ux500_ab85xx.c, for example. > > > > Hm I am trying to get that driver to work ... from time to time. > > It's just that ALSA SoC DT has changed to much that it turns out > > into a complete rewrite :/ > > > > So in sound/soc/ux500/mop500_ab8500.c > > I see this: > > > > status = clk_set_parent(drvdata->clk_ptr_intclk, clk_ptr); > > if (status) > > (...) > > > > and there is elaborate code to switch between "SYSCLK" and > > "ULPCLK" (ulta-low power clock). Just like you say... however > > a clock named SYSCLK or ULPCLK does not appear in the > > code in drivers/clk/ux500 or any DT bindings so... it seems to > > be non-working for the time being. > > It's definitely not working, but the corresponding clocks ("ulpclk", > "intclk", "audioclk", etc) are being registered in ab8500_reg_clks(). > > What seems to be missing is a DT conversion for these clocks, so they > can be consumed properly. Right? Yeps that and a few more things, I have a scratch rewrite here: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git/log/?h=ux500-audio-rewrite I remember Lee said he had audio working with the mainline kernel on Snowball at one point, unfortunately I think that was before we started with the DT conversions and then we probably broke it. Yours, Linus Walleij
On Fri, 11 Nov 2022, Linus Walleij wrote: > On Thu, Nov 10, 2022 at 2:05 PM Ulf Hansson <ulf.hansson@linaro.org> wrote: > > On Thu, 10 Nov 2022 at 12:39, Linus Walleij <linus.walleij@linaro.org> wrote: > > > > > > On Thu, Nov 10, 2022 at 12:29 PM Ulf Hansson <ulf.hansson@linaro.org> wrote: > > > > On Fri, 4 Nov 2022 at 14:32, Maxime Ripard <maxime@cerno.tech> wrote: > > > > > > > > > > The UX500 sysctrl "set_parent" clocks implement a mux with a set_parent > > > > > hook, but doesn't provide a determine_rate implementation. > > > > > > > > > > This is a bit odd, since set_parent() is there to, as its name implies, > > > > > change the parent of a clock. However, the most likely candidate to > > > > > trigger that parent change is a call to clk_set_rate(), with > > > > > determine_rate() figuring out which parent is the best suited for a > > > > > given rate. > > > > > > > > > > The other trigger would be a call to clk_set_parent(), but it's far less > > > > > used, and it doesn't look like there's any obvious user for that clock. > > > > > > > > If I recall correctly, that is the use case we did target for these > > > > types of clocks. See sound/soc/ux500/ux500_ab85xx.c, for example. > > > > > > Hm I am trying to get that driver to work ... from time to time. > > > It's just that ALSA SoC DT has changed to much that it turns out > > > into a complete rewrite :/ > > > > > > So in sound/soc/ux500/mop500_ab8500.c > > > I see this: > > > > > > status = clk_set_parent(drvdata->clk_ptr_intclk, clk_ptr); > > > if (status) > > > (...) > > > > > > and there is elaborate code to switch between "SYSCLK" and > > > "ULPCLK" (ulta-low power clock). Just like you say... however > > > a clock named SYSCLK or ULPCLK does not appear in the > > > code in drivers/clk/ux500 or any DT bindings so... it seems to > > > be non-working for the time being. > > > > It's definitely not working, but the corresponding clocks ("ulpclk", > > "intclk", "audioclk", etc) are being registered in ab8500_reg_clks(). > > > > What seems to be missing is a DT conversion for these clocks, so they > > can be consumed properly. Right? > > Yeps that and a few more things, I have a scratch rewrite here: > https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git/log/?h=ux500-audio-rewrite > > I remember Lee said he had audio working with the mainline kernel > on Snowball at one point, unfortunately I think that was before we > started with the DT conversions and then we probably broke it. That was also 100 years ago. :) But yes, it used to work at one point.
diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c index 702f2f8b43fa..d36336665b6d 100644 --- a/drivers/clk/ux500/clk-sysctrl.c +++ b/drivers/clk/ux500/clk-sysctrl.c @@ -110,6 +110,7 @@ static const struct clk_ops clk_sysctrl_gate_fixed_rate_ops = { }; static const struct clk_ops clk_sysctrl_set_parent_ops = { + .determine_rate = __clk_mux_determine_rate, .set_parent = clk_sysctrl_set_parent, .get_parent = clk_sysctrl_get_parent, }; @@ -220,6 +221,7 @@ struct clk *clk_reg_sysctrl_set_parent(struct device *dev, unsigned long flags) { return clk_reg_sysctrl(dev, name, parent_names, num_parents, - reg_sel, reg_mask, reg_bits, 0, 0, flags, + reg_sel, reg_mask, reg_bits, 0, 0, + flags | CLK_SET_RATE_NO_REPARENT, &clk_sysctrl_set_parent_ops); }
The UX500 sysctrl "set_parent" clocks implement a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the flag CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook to __clk_mux_determine_rate(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. __clk_mux_determine_rate() has the exact same behavior when CLK_SET_RATE_NO_REPARENT is set. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Signed-off-by: Maxime Ripard <maxime@cerno.tech> --- drivers/clk/ux500/clk-sysctrl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)