From patchwork Fri Nov 18 02:58:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bard Liao X-Patchwork-Id: 13047679 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BE72C4332F for ; Fri, 18 Nov 2022 02:57:40 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 762CF16DD; Fri, 18 Nov 2022 03:56:48 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 762CF16DD DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1668740258; bh=sFoTlN5v6r79HUZxzN2vBniRQPFO0vULAV0J7b3pGgI=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=WNEYUR6Ac0268cRpaq9CHSiYUQiXl8e1B4Tw4U4pYqfTILAlnbnoHWTuYT2U9BzIg keN/GyTg1DUN6lr8y36o5ENOhxpOvkbH8r1/wU+TmMbtLAFazw5cckmRBg3lo+yaM8 M6pAFn35QjUxQcvS7yB1HV1lNA9MBr/jCcT646CY= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id D8493F80559; Fri, 18 Nov 2022 03:56:01 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id E8934F80557; Fri, 18 Nov 2022 03:55:59 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 27CC6F8016E for ; Fri, 18 Nov 2022 03:55:52 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 27CC6F8016E Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GwHFAHYQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668740154; x=1700276154; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sFoTlN5v6r79HUZxzN2vBniRQPFO0vULAV0J7b3pGgI=; b=GwHFAHYQq/2+Vj6eLm/HWErJAXBiWArQANTxsdPnqLwpHBKTJZd2HnGl LHKLVEweTmKjPs/jqjUr4NjThufvX0hBKLDbjlQMYzNezHXVx/fP9jcK2 NWex2nmH+/CbdwAISmSmJwkJrRP6rTAQgT1vcnRI/CFERMzFlQWHMPUDk gGO7vrdrvE5s64sqrHYTaJNNB+wH1Sil3MiL78N+3govMdNcI/3HTXvhA 93MgPjfPLkzJMs6qyK6NLyR7LwUMrSRMHMbR7b/2BqzwlqJVvj8nc0Ewd HLkCGJ2IDVbqrrlvpb/SC9XUdTKig4KSmj1oAuT/f0H5Xnjxl8N52Lxpp A==; X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="399323297" X-IronPort-AV: E=Sophos;i="5.96,172,1665471600"; d="scan'208";a="399323297" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2022 18:55:50 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10534"; a="642347898" X-IronPort-AV: E=Sophos;i="5.96,172,1665471600"; d="scan'208";a="642347898" Received: from bard-ubuntu.sh.intel.com ([10.239.185.57]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2022 18:55:48 -0800 From: Bard Liao To: broonie@kernel.org, tiwai@suse.de Subject: [PATCH v2 2/2] soundwire: enable optional clock registers for SoundWire 1.2 devices Date: Fri, 18 Nov 2022 10:58:07 +0800 Message-Id: <20221118025807.534863-3-yung-chuan.liao@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221118025807.534863-1-yung-chuan.liao@linux.intel.com> References: <20221118025807.534863-1-yung-chuan.liao@linux.intel.com> MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, vinod.koul@linaro.org, linux-kernel@vger.kernel.org, pierre-louis.bossart@linux.intel.com, ranjani.sridharan@linux.intel.com, vkoul@kernel.org, peter.ujfalusi@linux.intel.com, bard.liao@intel.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Pierre-Louis Bossart The bus supports the mandatory clock registers for SDCA devices, these registers can also be optionally supported by SoundWire 1.2 devices that don't follow the SDCA class specification. Signed-off-by: Pierre-Louis Bossart Reviewed-by: Rander Wang Reviewed-by: Péter Ujfalusi Signed-off-by: Bard Liao Reviewed-by: Charles Keepax --- drivers/soundwire/bus.c | 7 ++++--- include/linux/soundwire/sdw.h | 4 ++++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/soundwire/bus.c b/drivers/soundwire/bus.c index c23275b443ac..55d393247a0f 100644 --- a/drivers/soundwire/bus.c +++ b/drivers/soundwire/bus.c @@ -1233,10 +1233,11 @@ static int sdw_slave_set_frequency(struct sdw_slave *slave) /* * frequency base and scale registers are required for SDCA - * devices. They may also be used for 1.2+/non-SDCA devices, - * but we will need a DisCo property to cover this case + * devices. They may also be used for 1.2+/non-SDCA devices. + * Driver can set the property, we will need a DisCo property + * to discover this case from platform firmware. */ - if (!slave->id.class_id) + if (!slave->id.class_id && !slave->prop.clock_reg_supported) return 0; if (!mclk_freq) { diff --git a/include/linux/soundwire/sdw.h b/include/linux/soundwire/sdw.h index 8fb458931772..9a49263c53cf 100644 --- a/include/linux/soundwire/sdw.h +++ b/include/linux/soundwire/sdw.h @@ -365,6 +365,9 @@ struct sdw_dpn_prop { * @sink_dpn_prop: Sink Data Port N properties * @scp_int1_mask: SCP_INT1_MASK desired settings * @quirks: bitmask identifying deltas from the MIPI specification + * @clock_reg_supported: the Peripheral implements the clock base and scale + * registers introduced with the SoundWire 1.2 specification. SDCA devices + * do not need to set this boolean property as the registers are required. */ struct sdw_slave_prop { u32 mipi_revision; @@ -388,6 +391,7 @@ struct sdw_slave_prop { struct sdw_dpn_prop *sink_dpn_prop; u8 scp_int1_mask; u32 quirks; + bool clock_reg_supported; }; #define SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY BIT(0)