Message ID | 20230515081301.12921-1-yung-chuan.liao@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | soundwire: intel: read AC timing control register before updating it | expand |
On 15-05-23, 16:13, Bard Liao wrote: > From: Chao Song <chao.song@linux.intel.com> > > Start from ACE1.x, DOAISE is added to AC timing control > register bit 5, it combines with DOAIS to get effective > timing, and has the default value 1. > > The current code fills DOAIS, DACTQE and DODS bits to a > variable initialized to zero, and updates the variable > to AC timing control register. With this operation, We > change DOAISE to 0, and force a much more aggressive > timing. The timing is even unable to form a working > waveform on SDA pin on Meteorlake. > > This patch uses read-modify-write operation for the AC > timing control register access, thus makes sure those > bits not supposed and intended to change are not touched. Applied, thanks
diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c index 238acf5c97a9..8cd2c73ac66f 100644 --- a/drivers/soundwire/intel.c +++ b/drivers/soundwire/intel.c @@ -260,7 +260,7 @@ static void intel_shim_init(struct sdw_intel *sdw) { void __iomem *shim = sdw->link_res->shim; unsigned int link_id = sdw->instance; - u16 ioctl = 0, act = 0; + u16 ioctl = 0, act; /* Initialize Shim */ ioctl |= SDW_SHIM_IOCTL_BKE; @@ -281,6 +281,7 @@ static void intel_shim_init(struct sdw_intel *sdw) intel_shim_glue_to_master_ip(sdw); + act = intel_readw(shim, SDW_SHIM_CTMCTL(link_id)); u16p_replace_bits(&act, 0x1, SDW_SHIM_CTMCTL_DOAIS); act |= SDW_SHIM_CTMCTL_DACTQE; act |= SDW_SHIM_CTMCTL_DODS;