| Message ID | 20230530103012.3448838-1-chancel.liu@nxp.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 32cf0046a652116d6a216d575f3049a9ff9dd80d |
| Headers | show |
| Series | ASoC: fsl_sai: Enable BCI bit if SAI works on synchronous mode with BYP asserted | expand |
On Tue, May 30, 2023 at 6:30 PM Chancel Liu <chancel.liu@nxp.com> wrote: > There's an issue on SAI synchronous mode that TX/RX side can't get BCLK > from RX/TX it sync with if BYP bit is asserted. It's a workaround to > fix it that enable SION of IOMUX pad control and assert BCI. > > For example if TX sync with RX which means both TX and RX are using clk > form RX and BYP=1. TX can get BCLK only if the following two conditions > are valid: > 1. SION of RX BCLK IOMUX pad is set to 1 > 2. BCI of TX is set to 1 > > Signed-off-by: Chancel Liu <chancel.liu@nxp.com> > Acked-by: Shengjiu Wang <shengjiu.wang@gmail.com> Best regards Wang Shengjiu > --- > sound/soc/fsl/fsl_sai.c | 11 +++++++++-- > sound/soc/fsl/fsl_sai.h | 1 + > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c > index d9344025dc16..5e09f634c61b 100644 > --- a/sound/soc/fsl/fsl_sai.c > +++ b/sound/soc/fsl/fsl_sai.c > @@ -491,14 +491,21 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, > bool tx, u32 freq) > regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, > FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); > > - if (savediv == 1) > + if (savediv == 1) { > regmap_update_bits(sai->regmap, reg, > FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, > FSL_SAI_CR2_BYP); > - else > + if (fsl_sai_dir_is_synced(sai, adir)) > + regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, > ofs), > + FSL_SAI_CR2_BCI, > FSL_SAI_CR2_BCI); > + else > + regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, > ofs), > + FSL_SAI_CR2_BCI, 0); > + } else { > regmap_update_bits(sai->regmap, reg, > FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, > savediv / 2 - 1); > + } > > if (sai->soc_data->max_register >= FSL_SAI_MCTL) { > /* SAI is in master mode at this point, so enable MCLK */ > diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h > index 3eb994aef36a..8254c3547b87 100644 > --- a/sound/soc/fsl/fsl_sai.h > +++ b/sound/soc/fsl/fsl_sai.h > @@ -116,6 +116,7 @@ > > /* SAI Transmit and Receive Configuration 2 Register */ > #define FSL_SAI_CR2_SYNC BIT(30) > +#define FSL_SAI_CR2_BCI BIT(28) > #define FSL_SAI_CR2_MSEL_MASK (0x3 << 26) > #define FSL_SAI_CR2_MSEL_BUS 0 > #define FSL_SAI_CR2_MSEL_MCLK1 BIT(26) > -- > 2.25.1 > >
On Tue, 30 May 2023 18:30:12 +0800, Chancel Liu wrote: > There's an issue on SAI synchronous mode that TX/RX side can't get BCLK > from RX/TX it sync with if BYP bit is asserted. It's a workaround to > fix it that enable SION of IOMUX pad control and assert BCI. > > For example if TX sync with RX which means both TX and RX are using clk > form RX and BYP=1. TX can get BCLK only if the following two conditions > are valid: > 1. SION of RX BCLK IOMUX pad is set to 1 > 2. BCI of TX is set to 1 > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next Thanks! [1/1] ASoC: fsl_sai: Enable BCI bit if SAI works on synchronous mode with BYP asserted commit: 32cf0046a652116d6a216d575f3049a9ff9dd80d All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index d9344025dc16..5e09f634c61b 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -491,14 +491,21 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_MSEL_MASK, FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); - if (savediv == 1) + if (savediv == 1) { regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, FSL_SAI_CR2_BYP); - else + if (fsl_sai_dir_is_synced(sai, adir)) + regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), + FSL_SAI_CR2_BCI, FSL_SAI_CR2_BCI); + else + regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs), + FSL_SAI_CR2_BCI, 0); + } else { regmap_update_bits(sai->regmap, reg, FSL_SAI_CR2_DIV_MASK | FSL_SAI_CR2_BYP, savediv / 2 - 1); + } if (sai->soc_data->max_register >= FSL_SAI_MCTL) { /* SAI is in master mode at this point, so enable MCLK */ diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 3eb994aef36a..8254c3547b87 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -116,6 +116,7 @@ /* SAI Transmit and Receive Configuration 2 Register */ #define FSL_SAI_CR2_SYNC BIT(30) +#define FSL_SAI_CR2_BCI BIT(28) #define FSL_SAI_CR2_MSEL_MASK (0x3 << 26) #define FSL_SAI_CR2_MSEL_BUS 0 #define FSL_SAI_CR2_MSEL_MCLK1 BIT(26)
There's an issue on SAI synchronous mode that TX/RX side can't get BCLK from RX/TX it sync with if BYP bit is asserted. It's a workaround to fix it that enable SION of IOMUX pad control and assert BCI. For example if TX sync with RX which means both TX and RX are using clk form RX and BYP=1. TX can get BCLK only if the following two conditions are valid: 1. SION of RX BCLK IOMUX pad is set to 1 2. BCI of TX is set to 1 Signed-off-by: Chancel Liu <chancel.liu@nxp.com> --- sound/soc/fsl/fsl_sai.c | 11 +++++++++-- sound/soc/fsl/fsl_sai.h | 1 + 2 files changed, 10 insertions(+), 2 deletions(-)