From patchwork Thu Jul 20 11:29:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nikita Shubin via B4 Relay X-Patchwork-Id: 13321590 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 39484EB64DC for ; Fri, 21 Jul 2023 08:17:04 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 50C911FE; Fri, 21 Jul 2023 10:16:12 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 50C911FE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1689927422; bh=xLR/4GT6D6YFLFeHrRAjNQb14af/TnQhvn4EJhbCOIM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:List-Id: List-Archive:List-Help:List-Owner:List-Post:List-Subscribe: List-Unsubscribe:From; b=gj66mf+T/5/1EUNL4suzMhKwCvOqM11JpfX41aTC5W7fqzn/vVtMhDWPtdY2o6StH HwiwpH58Js0pazRTIWsAQ24wxrlDCGPAnuoDhkRwCxkG23BLeJrFLTVJfJPHdtqFBl Tf/5iX85LtEJ+94kSfevzhOd/BiTabaRgVM/zLmc= Received: by alsa1.perex.cz (Postfix, from userid 50401) id C6305F80692; Fri, 21 Jul 2023 10:10:35 +0200 (CEST) Received: from mailman-core.alsa-project.org (mailman-core.alsa-project.org [10.254.200.10]) by alsa1.perex.cz (Postfix) with ESMTP id 4803FF80691; Fri, 21 Jul 2023 10:10:35 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id D267CF804DA; Thu, 20 Jul 2023 10:30:48 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 9EA57F80568 for ; Thu, 20 Jul 2023 10:30:12 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 9EA57F80568 Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key, unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20201202 header.b=itvDN2Om Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id EA7E361BB6; Thu, 20 Jul 2023 08:30:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPS id 178E4C32783; Thu, 20 Jul 2023 08:29:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689841798; bh=xLR/4GT6D6YFLFeHrRAjNQb14af/TnQhvn4EJhbCOIM=; h=From:Date:Subject:References:In-Reply-To:List-Id:To:Cc:Reply-To: From; b=itvDN2OmCBG1gI3lJyUyGa1jn7YtcMD1nDvQXuf88MZKuENXFYCd66K5P2Iell7eS xXioSFxjbBUVeXsMh0dzi68FvWpfy/nOYv4LUhnEdjiPdeXBVJ4NU1JENOwMLi45g1 bqjAYu/NcT3B7u96F0uJFmTS//UwIQziq3+4eWacVwevmIcIbyQ9/dPE3b3mikR6mi ZwyV/ET40CNW/zvGjWssJIrO48y+TRVMw0nM3TnGZbVEMRex7l2h8TxA4S9xZ8KpGa N/OKQINaEeeEbsgPrG4aqQID4aG4pWvHr9lNUY7jvmrukDU60BdnXzfdZnloyCU562 LPX7k2EHmI19w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F4082C3DA40; Thu, 20 Jul 2023 08:29:57 +0000 (UTC) From: Nikita Shubin via B4 Relay Date: Thu, 20 Jul 2023 14:29:24 +0300 Subject: [PATCH v3 24/42] mtd: nand: add support for ts72xx MIME-Version: 1.0 Message-Id: <20230605-ep93xx-v3-24-3d63a5f1103e@maquefel.me> References: <20230605-ep93xx-v3-0-3d63a5f1103e@maquefel.me> In-Reply-To: <20230605-ep93xx-v3-0-3d63a5f1103e@maquefel.me> To: Hartley Sweeten , Lennert Buytenhek , Alexander Sverdlin , Russell King , Lukasz Majewski , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Nikita Shubin , Daniel Lezcano , Thomas Gleixner , Alessandro Zummo , Alexandre Belloni , Wim Van Sebroeck , Guenter Roeck , Sebastian Reichel , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Mark Brown , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vinod Koul , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Damien Le Moal , Sergey Shtylyov , Dmitry Torokhov , Arnd Bergmann , Olof Johansson , soc@kernel.org, Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Andy Shevchenko , Michael Peters , Kris Bahnsen Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-rtc@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-pm@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org, netdev@vger.kernel.org, dmaengine@vger.kernel.org, linux-mtd@lists.infradead.org, linux-ide@vger.kernel.org, linux-input@vger.kernel.org, alsa-devel@alsa-project.org X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1689852591; l=6240; i=nikita.shubin@maquefel.me; s=20230718; h=from:subject:message-id; bh=Mcu6XOIf27yl88yMJ5DKfoy1TYVtY2ZKrsI332LEqWY=; =?utf-8?q?b=3DagIHcFgVQ6/W?= =?utf-8?q?ooTScGYRbLZmnJx4lcPMV2ZI2i1PBOFs1khTbLgzmhSfDkx+Tm1D7FU/mlonQAnm?= I7nxdzTrBj3rbtk+lQxGvAQ6CqMSsiVhdplTvJ95p8Eo6QhG7NhM X-Developer-Key: i=nikita.shubin@maquefel.me; a=ed25519; pk=vqf5YIUJ7BJv3EJFaNNxWZgGuMgDH6rwufTLflwU9ac= X-Endpoint-Received: by B4 Relay for nikita.shubin@maquefel.me/20230718 with auth_id=65 X-Original-From: Nikita Shubin X-MailFrom: devnull+nikita.shubin.maquefel.me@kernel.org X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1 Message-ID-Hash: 5NOX6LII7VZKX23NMCFPR4BJWON6UFFR X-Message-ID-Hash: 5NOX6LII7VZKX23NMCFPR4BJWON6UFFR X-Mailman-Approved-At: Fri, 21 Jul 2023 08:10:31 +0000 X-Mailman-Version: 3.3.8 Precedence: list Reply-To: nikita.shubin@maquefel.me List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: From: Nikita Shubin Technologic Systems has it's own nand controller implementation in CPLD. Signed-off-by: Nikita Shubin --- drivers/mtd/nand/raw/Kconfig | 7 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/technologic-nand-controller.c | 162 +++++++++++++++++++++ 3 files changed, 170 insertions(+) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index b523354dfb00..94788da1a169 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -456,6 +456,13 @@ config MTD_NAND_RENESAS Enables support for the NAND controller found on Renesas R-Car Gen3 and RZ/N1 SoC families. +config MTD_NAND_TS72XX + bool "ts72xx NAND controller" + depends on ARCH_EP93XX && HAS_IOMEM + help + Enables support for NAND controller on ts72xx SBCs. + This is a legacy driver based on gen_nand. + comment "Misc" config MTD_SM_COMMON diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index d93e861d8ba7..b85161c3296b 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -23,6 +23,7 @@ omap2_nand-objs := omap2.o obj-$(CONFIG_MTD_NAND_OMAP2) += omap2_nand.o obj-$(CONFIG_MTD_NAND_OMAP_BCH_BUILD) += omap_elm.o obj-$(CONFIG_MTD_NAND_MARVELL) += marvell_nand.o +obj-$(CONFIG_MTD_NAND_TS72XX) += technologic-nand-controller.o obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o diff --git a/drivers/mtd/nand/raw/technologic-nand-controller.c b/drivers/mtd/nand/raw/technologic-nand-controller.c new file mode 100644 index 000000000000..c6a656210099 --- /dev/null +++ b/drivers/mtd/nand/raw/technologic-nand-controller.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Technologic Systems TS72xx NAND controller driver + * + * Copyright (C) 2023 Nikita Shubin + * + * Derived from: plat_nand.c + * Author: Vitaly Wool + */ + +#include +#include +#include +#include +#include + +#include +#include + +#define TS72XX_NAND_CONTROL_ADDR_LINE 22 /* 0xN0400000 */ +#define TS72XX_NAND_BUSY_ADDR_LINE 23 /* 0xN0800000 */ + +struct ts72xx_nand_data { + struct nand_controller controller; + struct nand_chip chip; + void __iomem *io_base; +}; + +static int ts72xx_nand_attach_chip(struct nand_chip *chip) +{ + switch (chip->ecc.engine_type) { + case NAND_ECC_ENGINE_TYPE_SOFT: + if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; + break; + case NAND_ECC_ENGINE_TYPE_ON_HOST: + return -EINVAL; + default: + break; + } + + return 0; +} + +static const struct nand_controller_ops ts72xx_nand_ops = { + .attach_chip = ts72xx_nand_attach_chip, +}; + +static void ts72xx_nand_hwcontrol(struct nand_chip *chip, + int cmd, unsigned int ctrl) +{ + if (ctrl & NAND_CTRL_CHANGE) { + void __iomem *addr = chip->legacy.IO_ADDR_R; + unsigned char bits; + + addr += BIT(TS72XX_NAND_CONTROL_ADDR_LINE); + + bits = readb(addr) & ~GENMASK(2, 0); + bits |= (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ + bits |= (ctrl & NAND_CLE); /* bit 1 -> bit 1 */ + bits |= (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ + + writeb(bits, addr); + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, chip->legacy.IO_ADDR_W); +} + +static int ts72xx_nand_device_ready(struct nand_chip *chip) +{ + void __iomem *addr = chip->legacy.IO_ADDR_R; + + addr += BIT(TS72XX_NAND_BUSY_ADDR_LINE); + + return !!(readb(addr) & BIT(5)); +} + +static int ts72xx_nand_probe(struct platform_device *pdev) +{ + struct ts72xx_nand_data *data; + struct device_node *child; + struct mtd_info *mtd; + int err; + + /* Allocate memory for the device structure (and zero it) */ + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->controller.ops = &ts72xx_nand_ops; + nand_controller_init(&data->controller); + data->chip.controller = &data->controller; + + data->io_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->io_base)) + return PTR_ERR(data->io_base); + + child = of_get_next_child(pdev->dev.of_node, NULL); + if (!child) + return dev_err_probe(&pdev->dev, -ENXIO, + "ts72xx controller node should have exactly one child\n"); + + nand_set_flash_node(&data->chip, child); + mtd = nand_to_mtd(&data->chip); + mtd->dev.parent = &pdev->dev; + + data->chip.legacy.IO_ADDR_R = data->io_base; + data->chip.legacy.IO_ADDR_W = data->io_base; + data->chip.legacy.cmd_ctrl = ts72xx_nand_hwcontrol; + data->chip.legacy.dev_ready = ts72xx_nand_device_ready; + + platform_set_drvdata(pdev, data); + + /* + * This driver assumes that the default ECC engine should be TYPE_SOFT. + * Set ->engine_type before registering the NAND devices in order to + * provide a driver specific default value. + */ + data->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; + + /* Scan to find existence of the device */ + err = nand_scan(&data->chip, 1); + if (err) + return err; + + err = mtd_device_parse_register(mtd, NULL, NULL, NULL, 0); + if (err) { + nand_cleanup(&data->chip); + return err; + } + + return 0; +} + +static void ts72xx_nand_remove(struct platform_device *pdev) +{ + struct ts72xx_nand_data *data = platform_get_drvdata(pdev); + struct nand_chip *chip = &data->chip; + int ret; + + ret = mtd_device_unregister(nand_to_mtd(chip)); + WARN_ON(ret); + nand_cleanup(chip); +} + +static const struct of_device_id ts72xx_id_table[] = { + { .compatible = "technologic,ts7200-nand" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ts72xx_id_table); + +static struct platform_driver ts72xx_nand_driver = { + .driver = { + .name = "ts72xx-nand", + .of_match_table = ts72xx_id_table, + }, + .probe = ts72xx_nand_probe, + .remove_new = ts72xx_nand_remove, +}; +module_platform_driver(ts72xx_nand_driver); +