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Mon, 12 Jun 2023 18:53:52 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 12 Jun 2023 18:53:51 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 12 Jun 2023 18:53:51 +0800 From: Maso Hunag To: AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai , Trevor Wu , Jiaxin Yu , Ren Zhijie , Arnd Bergmann , Allen-KH Cheng , , , , , CC: Maso Huang Subject: [PATCH 7/7] ASoC: dt-bindings: mediatek,mt79xx-afe: add audio afe document Date: Mon, 12 Jun 2023 18:52:50 +0800 Message-ID: <20230612105250.15441-8-maso.huang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230612105250.15441-1-maso.huang@mediatek.com> References: <20230612105250.15441-1-maso.huang@mediatek.com> MIME-Version: 1.0 X-MailFrom: maso.huang@mediatek.com X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1 Message-ID-Hash: 5XJGM377S37QPITNWBUGNRIHFTQ7MCIY X-Message-ID-Hash: 5XJGM377S37QPITNWBUGNRIHFTQ7MCIY X-Mailman-Approved-At: Mon, 12 Jun 2023 15:32:08 +0000 X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: From: Maso Huang Add mt79xx audio afe document. Signed-off-by: Maso Huang --- .../bindings/sound/mediatek,mt79xx-afe.yaml | 102 ++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt79xx-afe.yaml diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt79xx-afe.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt79xx-afe.yaml new file mode 100644 index 000000000000..11ef1cfdf49b --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt79xx-afe.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt79xx-afe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek AFE PCM controller for MT79xx + +maintainers: + - Maso Huang + +properties: + compatible: + oneOf: + - const: mediatek,mt79xx-afe + - items: + - enum: + - mediatek,mt7981-afe + - mediatek,mt7986-afe + - mediatek,mt7988-afe + - const: mediatek,mt79xx-afe + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 5 + items: + - description: audio bus clock + - description: audio 26M clock + - description: audio intbus clock + - description: audio hopping clock + - description: audio pll clock + - description: mux for pcm_mck + - description: audio i2s/pcm mck + + clock-names: + minItems: 5 + items: + - const: aud_bus_ck + - const: aud_26m_ck + - const: aud_l_ck + - const: aud_aud_ck + - const: aud_eg2_ck + - const: aud_sel + - const: aud_i2s_m + + assigned-clocks: + minItems: 3 + maxItems: 4 + + assigned-clock-parents: + minItems: 3 + maxItems: 4 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - assigned-clocks + - assigned-clock-parents + +additionalProperties: false + +examples: + - | + #include + #include + #include + + afe@11210000 { + compatible = "mediatek,mt7981-afe","mediatek,mt79xx-afe"; + reg = <0x11210000 0x9000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AUD_BUS_CK>, + <&infracfg_ao CLK_INFRA_AUD_26M_CK>, + <&infracfg_ao CLK_INFRA_AUD_L_CK>, + <&infracfg_ao CLK_INFRA_AUD_AUD_CK>, + <&infracfg_ao CLK_INFRA_AUD_EG2_CK>, + <&topckgen CLK_TOP_AUD_SEL>; + clock-names = "aud_bus_ck", + "aud_26m_ck", + "aud_l_ck", + "aud_aud_ck", + "aud_eg2_ck", + "aud_sel"; + assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, + <&topckgen CLK_TOP_A1SYS_SEL>, + <&topckgen CLK_TOP_AUD_L_SEL>, + <&topckgen CLK_TOP_A_TUNER_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>, + <&topckgen CLK_TOP_APLL2_D4>, + <&topckgen CLK_TOP_CB_APLL2_196M>, + <&topckgen CLK_TOP_APLL2_D4>; + }; + +...