From patchwork Fri Jun 23 20:30:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varshini Rajendran X-Patchwork-Id: 13292721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B59DAEB64D7 for ; Mon, 26 Jun 2023 11:31:44 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id B5FC9DEB; Mon, 26 Jun 2023 13:30:52 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz B5FC9DEB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1687779102; bh=xbMFJDkuvSAVzLORTJHW0ZL04qI1N0hFjbaAsJ5qgb0=; h=From:To:CC:Subject:Date:In-Reply-To:References:List-Id: List-Archive:List-Help:List-Owner:List-Post:List-Subscribe: List-Unsubscribe:From; b=QeCgMhkQvf9lpW4QcFlyDpNDYOsvZkTMPzZuJmA3hqPcea4PsCNPZlPn8wjD3HVFq djbReDu7n9lVbW5jad72JlXlRiJ915+x3facKIpS3tKzpG3TnM3FxyeePlUyIeY6HF sGFtmuLgCx/Pjxy85tmAt5FVxWmXvH27zxQZ+b7A= Received: by alsa1.perex.cz (Postfix, from userid 50401) id 3B012F80612; Mon, 26 Jun 2023 13:27:35 +0200 (CEST) Received: from mailman-core.alsa-project.org (mailman-core.alsa-project.org [10.254.200.10]) by alsa1.perex.cz (Postfix) with ESMTP id 832B1F80611; Mon, 26 Jun 2023 13:27:35 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 6D7AEF80141; Fri, 23 Jun 2023 22:49:37 +0200 (CEST) Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 35C0EF8003A for ; Fri, 23 Jun 2023 22:49:33 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 35C0EF8003A Authentication-Results: alsa1.perex.cz; dkim=pass (2048-bit key, unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=I/ubcycp DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1687553375; x=1719089375; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xbMFJDkuvSAVzLORTJHW0ZL04qI1N0hFjbaAsJ5qgb0=; b=I/ubcycpXbm/fsDB9mgN+/bYDMfM8HHy+0GJk2BpCTM2HZYgWqPUrAdU WQf1j/13Fkxu99GKNW5ox9QQ1jk/qUYyzsf9HKegitCMU2N7sYva0FNPt vPCC7eA/UzennXeaY8Ioa3Nvz43aviD9QnEFP7+jNnTI4bFruXRUe0iAm MhrvHarT5dC4FsfBgGa1n3LzVdkPypq0r199szxF35rU3AchvIdxl8+qN hlqndix0p0sW3JJJw8je5zvM2NTtaceC1+SZLCnqr8s2RldGvP6QZ0pf3 QLWFBUzEFStWrFIbvnW2hpo+zlpp4T4SQCMT4X0M1EUyqXR5FYcC+A2m8 A==; X-IronPort-AV: E=Sophos;i="6.01,153,1684825200"; d="scan'208";a="221703169" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Jun 2023 13:49:30 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 23 Jun 2023 13:49:30 -0700 Received: from che-lt-i67070.amer.actel.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Fri, 23 Jun 2023 13:49:01 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , Subject: [PATCH v2 37/45] irqchip/atmel-aic5: Add support for sam9x7 aic Date: Sat, 24 Jun 2023 02:00:48 +0530 Message-ID: <20230623203056.689705-38-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230623203056.689705-1-varshini.rajendran@microchip.com> References: <20230623203056.689705-1-varshini.rajendran@microchip.com> MIME-Version: 1.0 X-MailFrom: Varshini.Rajendran@microchip.com X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1 Message-ID-Hash: FKX2EAKIU4ETRCDESNSXHH2FQ6SNPZ3A X-Message-ID-Hash: FKX2EAKIU4ETRCDESNSXHH2FQ6SNPZ3A X-Mailman-Approved-At: Mon, 26 Jun 2023 11:27:25 +0000 X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: From: Hari Prasath Add support for the Advanced interrupt controller(AIC) chip in the sam9x7. Signed-off-by: Hari Prasath Signed-off-by: Varshini Rajendran --- drivers/irqchip/irq-atmel-aic5.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c index 145535bd7560..bab11900f3ef 100644 --- a/drivers/irqchip/irq-atmel-aic5.c +++ b/drivers/irqchip/irq-atmel-aic5.c @@ -320,6 +320,7 @@ static const struct of_device_id aic5_irq_fixups[] __initconst = { { .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup }, { .compatible = "atmel,sama5d4", .data = sama5d3_aic_irq_fixup }, { .compatible = "microchip,sam9x60", .data = sam9x60_aic_irq_fixup }, + { .compatible = "microchip,sam9x7", .data = sam9x60_aic_irq_fixup }, { /* sentinel */ }, }; @@ -406,3 +407,12 @@ static int __init sam9x60_aic5_of_init(struct device_node *node, return aic5_of_init(node, parent, NR_SAM9X60_IRQS); } IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init); + +#define NR_SAM9X7_IRQS 70 + +static int __init sam9x7_aic5_of_init(struct device_node *node, + struct device_node *parent) +{ + return aic5_of_init(node, parent, NR_SAM9X7_IRQS); +} +IRQCHIP_DECLARE(sam9x7_aic5, "microchip,sam9x7-aic", sam9x7_aic5_of_init);