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Mon, 26 Jun 2023 05:49:44 -0500 Received: from vijendar-X570-GAMING-X.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Mon, 26 Jun 2023 05:49:41 -0500 From: Vijendar Mukunda To: CC: , , , , , Vijendar Mukunda , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , open list Subject: [PATCH 4/6] ASoC: amd: ps: add comments for DMA register mapping Date: Mon, 26 Jun 2023 16:23:52 +0530 Message-ID: <20230626105356.2580125-4-Vijendar.Mukunda@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230626105356.2580125-1-Vijendar.Mukunda@amd.com> References: <20230626105356.2580125-1-Vijendar.Mukunda@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT034:EE_|PH0PR12MB5605:EE_ X-MS-Office365-Filtering-Correlation-Id: 5f9d07b0-afac-4be7-603f-08db76330dbb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tRnkt7IiMO1Idy48RDSxRzDAzKFvAXcWpVWWDwFXpOGfIMaNrILdZEZLscKgnrs/9HqXfNgVb8Jelq3/yowIW27+F3cGJk1xhbXqbJh2M8geYk9vnmVs1qViDiHsS3cANpitpOdiH8nBiUk4bi7usLbVDdHiM4XtQWIz14NGS1ydN9/6iIHefANQ3lpgfdU6LtTMO6UY6chWrW5hgDuhudch2fWclUR+ui8cxpcNllkTIt2g5LbdYWUfUpQmGTnHQabATr6Ea04qMjIGZyoBv9JA6W36uw7CleO1Qucvz9tnB/Uvf88vCHL4lM5/yPAeUeuDmKt5O19V6/GllScURiVklg5EvcTtWApHiFYztoRESBm1V9LINo3gEeVe0H/kPOL1jNpPwKmvcUxRQJ6jBQVTc34xNXaCWZMbMsfDiiwgw30UIfp9u9nnz7p88CULb5WVSq3BkWJ7z0VxK4S44I90HvZqMmbf7d6+Fy4fj5Vdj4zjxaXKtjVanvpGj+ABdmKQRrijanIAh8A2iik3Fw1ToUy3DTAVVH/q9Kjv+OMZ9JEH8b7ePenW7qQ+tDGVJeWAjhNejjOxN+yC9jxsELkXUT6cFz5TCBPnIcezgVvq1fl9xs3iuJQYiASo+EqkckgkXibsVbQ7yVEbhw/ZRF5W3uKILc99TXwvKdGs9Si7TSbh2ouy7egxtZfxF/9Ae+fzUUeFBBRWJGa4CDx3WuJKXqj8XDKwIBk+pQcBcmKMTiw1Am5VybgP0UWpo29Uu6p6j88hXbB6suA2yFA6Xg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(346002)(136003)(39860400002)(396003)(376002)(451199021)(40470700004)(36840700001)(46966006)(82310400005)(36860700001)(47076005)(6666004)(2616005)(7696005)(336012)(426003)(54906003)(26005)(1076003)(186003)(2906002)(478600001)(5660300002)(36756003)(40460700003)(70206006)(356005)(81166007)(70586007)(82740400003)(40480700001)(4326008)(316002)(8936002)(8676002)(41300700001)(86362001)(6916009)(36900700001);DIR:OUT;SFP:1101; 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nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: <> List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: Add comments for DMA register mapping for both the SoundWire manager instances. Signed-off-by: Vijendar Mukunda --- sound/soc/amd/ps/ps-sdw-dma.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/sound/soc/amd/ps/ps-sdw-dma.c b/sound/soc/amd/ps/ps-sdw-dma.c index 3ab41bd1fce2..000ab5d96815 100644 --- a/sound/soc/amd/ps/ps-sdw-dma.c +++ b/sound/soc/amd/ps/ps-sdw-dma.c @@ -39,6 +39,11 @@ static struct sdw_dma_ring_buf_reg sdw0_dma_ring_buf_reg[ACP63_SDW0_DMA_MAX_STRE ACP_AUDIO2_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH} }; +/* + * SDW1 instance supports one TX stream and one RX stream. + * For TX/RX streams DMA registers programming for SDW1 instance, it uses ACP_P1_AUDIO1 register + * set as per hardware register documentation + */ static struct sdw_dma_ring_buf_reg sdw1_dma_ring_buf_reg[ACP63_SDW1_DMA_MAX_STREAMS] = { {ACP_P1_AUDIO1_TX_DMA_SIZE, ACP_P1_AUDIO1_TX_FIFOADDR, ACP_P1_AUDIO1_TX_FIFOSIZE, ACP_P1_AUDIO1_TX_RINGBUFSIZE, ACP_P1_AUDIO1_TX_RINGBUFADDR, @@ -59,6 +64,12 @@ static u32 sdw0_dma_enable_reg[ACP63_SDW0_DMA_MAX_STREAMS] = { ACP_SW0_AUDIO2_RX_EN, }; +/* + * SDW1 instance supports one TX stream and one RX stream. + * For TX/RX streams DMA enable register programming for SDW1 instance, + * it uses ACP_SW1_AUDIO1_TX_EN and ACP_SW1_AUDIO1_RX_EN registers + * as per hardware register documentation. + */ static u32 sdw1_dma_enable_reg[ACP63_SDW1_DMA_MAX_STREAMS] = { ACP_SW1_AUDIO1_TX_EN, ACP_SW1_AUDIO1_RX_EN,