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Wed, 20 Mar 2024 09:02:47 +0000 Received: from NTZPR01MB0956.CHNPR01.prod.partner.outlook.cn ([fe80::7d98:f313:525d:fea6]) by NTZPR01MB0956.CHNPR01.prod.partner.outlook.cn ([fe80::7d98:f313:525d:fea6%6]) with mapi id 15.20.7386.022; Wed, 20 Mar 2024 09:02:47 +0000 From: Xingyu Wu To: Liam Girdwood , Mark Brown , Claudiu Beznea , Jaroslav Kysela , Takashi Iwai , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Xingyu Wu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, linux-sound@vger.kernel.org Subject: [PATCH v2 1/2] ASoC: dt-bindings: Add bindings for Cadence I2S-MC controller Date: Wed, 20 Mar 2024 17:02:38 +0800 Message-Id: <20240320090239.168743-2-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240320090239.168743-1-xingyu.wu@starfivetech.com> References: <20240320090239.168743-1-xingyu.wu@starfivetech.com> X-ClientProxiedBy: SHXPR01CA0025.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1b::34) To NTZPR01MB0956.CHNPR01.prod.partner.outlook.cn (2406:e500:c510:8::10) Precedence: bulk X-Mailing-List: linux-sound@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: NTZPR01MB0956:EE_|NTZPR01MB1034:EE_ X-MS-Office365-Filtering-Correlation-Id: 3b3ed185-51f4-4976-8be4-08dc48bc832a X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; 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The Multi-Channel I2S (I2S-MC) implements a function of the 8-channel I2S bus interfasce. Each channel can become receiver or transmitter. Four I2S instances are used on the StarFive JH8100 SoC. One instance of them is limited to 2 channels, two instance are limited to 4 channels, and the other one can use most 8 channels. Add a unique property about 'starfive,i2s-max-channels' to distinguish each instance. Signed-off-by: Xingyu Wu --- .../bindings/sound/cdns,i2s-mc.yaml | 110 ++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/cdns,i2s-mc.yaml diff --git a/Documentation/devicetree/bindings/sound/cdns,i2s-mc.yaml b/Documentation/devicetree/bindings/sound/cdns,i2s-mc.yaml new file mode 100644 index 000000000000..0a1b0122a246 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cdns,i2s-mc.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/cdns,i2s-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence multi-channel I2S controller + +description: + The Cadence I2S Controller implements a function of the multi-channel + (up to 8-channel) bus. It combines functions of a transmitter and a receiver. + +maintainers: + - Xingyu Wu + +properties: + compatible: + enum: + - cdns,i2s-mc + - starfive,jh8100-i2s + + reg: + maxItems: 1 + + interrupts: + description: + The interrupt line number for the I2S controller. Add this + parameter if the I2S controller that you are using does not + using DMA. + maxItems: 1 + + clocks: + items: + - description: Bit clock + - description: Main ICG clock + - description: Inner master clock + + clock-names: + items: + - const: bclk + - const: icg + - const: mclk_inner + + resets: + maxItems: 1 + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + minItems: 1 + + dma-names: + items: + - const: tx + - const: rx + minItems: 1 + + "#sound-dai-cells": + const: 0 + +allOf: + - $ref: dai-common.yaml# + - if: + properties: + compatible: + contains: + const: starfive,jh8100-i2s + then: + properties: + starfive,i2s-max-channels: + description: + Number of I2S max stereo channels supported on the StarFive + JH8100 SoC. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2, 4, 8] + required: + - starfive,i2s-max-channels + +required: + - compatible + - reg + - clocks + - clock-names + - resets + +oneOf: + - required: + - dmas + - dma-names + - required: + - interrupts + +unevaluatedProperties: false + +examples: + - | + i2s@122b0000 { + compatible = "cdns,i2s-mc"; + reg = <0x122b0000 0x1000>; + clocks = <&syscrg_ne 133>, + <&syscrg_ne 170>, + <&syscrg 50>; + clock-names = "bclk", "icg", + "mclk_inner"; + resets = <&syscrg_ne 43>; + dmas = <&dma 7>, <&dma 6>; + dma-names = "tx", "rx"; + #sound-dai-cells = <0>; + };