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Some sample rates are not supported. If the PLL source is used for 8kHz series rates, then 11kHz series rates can't be supported. Use fsl_asoc_constrain_rates() to constrain rates according to PLL sources. Signed-off-by: Chancel Liu --- sound/soc/fsl/fsl_sai.c | 7 ++++++- sound/soc/fsl/fsl_sai.h | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 634168d2bb6e..c4eb87c5d39e 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -885,7 +885,7 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream, sai->dma_params_rx.maxburst); ret = snd_pcm_hw_constraint_list(substream->runtime, 0, - SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); + SNDRV_PCM_HW_PARAM_RATE, &sai->constraint_rates); return ret; } @@ -1442,6 +1442,11 @@ static int fsl_sai_probe(struct platform_device *pdev) fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, &sai->pll11k_clk); + fsl_asoc_constrain_rates(&sai->constraint_rates, + &fsl_sai_rate_constraints, + sai->pll8k_clk, sai->pll11k_clk, NULL, + sai->constraint_rates_list); + /* Use Multi FIFO mode depending on the support from SDMA script */ ret = of_property_read_u32_array(np, "dmas", dmas, 4); if (!sai->soc_data->use_edma && !ret && dmas[2] == IMX_DMATYPE_MULTI_SAI) diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 9c4d19fe22c6..0e25e2fc7ce0 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -9,6 +9,7 @@ #include #include +#define FAL_SAI_NUM_RATES 20 #define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ SNDRV_PCM_FMTBIT_S20_3LE |\ SNDRV_PCM_FMTBIT_S24_LE |\ @@ -309,6 +310,8 @@ struct fsl_sai { struct pinctrl *pinctrl; struct pinctrl_state *pins_state; struct sdma_peripheral_config audio_config[2]; + struct snd_pcm_hw_constraint_list constraint_rates; + unsigned int constraint_rates_list[FAL_SAI_NUM_RATES]; }; #define TX 1