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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jan 2025 10:14:04.3557 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3a9eac20-5ee5-4316-8f32-08dd393b2b06 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36E.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9480 Set ACP_PME_EN to 1 during runtime suspend sequence as per design flow for ACP7.0 & ACP7.1 platforms. Signed-off-by: Vijendar Mukunda --- drivers/soundwire/amd_manager.c | 9 +++++++++ drivers/soundwire/amd_manager.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/soundwire/amd_manager.c b/drivers/soundwire/amd_manager.c index 42d553878e91..03c9e15dce5b 100644 --- a/drivers/soundwire/amd_manager.c +++ b/drivers/soundwire/amd_manager.c @@ -1215,6 +1215,7 @@ static int __maybe_unused amd_suspend_runtime(struct device *dev) struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev); struct sdw_bus *bus = &amd_manager->bus; int ret; + u32 val; if (bus->prop.hw_disabled) { dev_dbg(bus->dev, "SoundWire manager %d is disabled,\n", @@ -1239,6 +1240,14 @@ static int __maybe_unused amd_suspend_runtime(struct device *dev) ret = amd_sdw_set_device_state(amd_manager, AMD_SDW_DEVICE_STATE_D3); if (ret) return ret; + if (amd_manager->wake_en_mask) { + val = readl(amd_manager->acp_mmio + ACP_PME_EN); + if (!val) { + writel(1, amd_manager->acp_mmio + ACP_PME_EN); + val = readl(amd_manager->acp_mmio + ACP_PME_EN); + dev_dbg(amd_manager->dev, "ACP_PME_EN:0x%x\n", val); + } + } } return 0; } diff --git a/drivers/soundwire/amd_manager.h b/drivers/soundwire/amd_manager.h index 8430f279d88e..1d5e94371f81 100644 --- a/drivers/soundwire/amd_manager.h +++ b/drivers/soundwire/amd_manager.h @@ -199,6 +199,7 @@ #define AMD_SDW1_DEVICE_STATE_MASK GENMASK(3, 2) #define AMD_SDW_DEVICE_STATE_D0 0 #define AMD_SDW_DEVICE_STATE_D3 3 +#define ACP_PME_EN 0x0001400 static u32 amd_sdw_freq_tbl[AMD_SDW_MAX_FREQ_NUM] = { AMD_SDW_DEFAULT_CLK_FREQ,