From patchwork Mon Nov 22 15:54:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 12633685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D9873C433EF for ; Tue, 23 Nov 2021 08:23:05 +0000 (UTC) Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id CB78B166F; Tue, 23 Nov 2021 09:22:13 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz CB78B166F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1637655783; bh=VEUWD0CxZ46HtswBQJr7JZjqpwBszi5zhI6fF/ugNPo=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=Vzu5U8Z3lt8+OrHcmRJN0O4XGwTGPpf/pzWxC/7sjBSI0QYMESDVzFlT42rhnfc45 E9ofKKB3Wxk9BX75bO+MuaQTP+aXtyGzxabJbqr1pqTcnWU7uHBrrHeAYmCF5oN3rQ 921ER8jwmophpiis7I1abynFuniFe4aW/Xi7IPM4= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 845F7F804F2; Tue, 23 Nov 2021 09:21:10 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id EC969F804E3; Mon, 22 Nov 2021 16:55:44 +0100 (CET) Received: from laurent.telenet-ops.be (laurent.telenet-ops.be [IPv6:2a02:1800:110:4::f00:19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id CEFB6F80154 for ; Mon, 22 Nov 2021 16:55:38 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz CEFB6F80154 Received: from ramsan.of.borg ([IPv6:2a02:1810:ac12:ed20:e4da:38c:79e9:48bf]) by laurent.telenet-ops.be with bizsmtp id MTux2600K4yPVd601Tuxk9; Mon, 22 Nov 2021 16:55:38 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.93) (envelope-from ) id 1mpBe6-00EL3j-Vr; Mon, 22 Nov 2021 16:54:18 +0100 Received: from geert by rox.of.borg with local (Exim 4.93) (envelope-from ) id 1mpBe5-00HGzT-Qs; Mon, 22 Nov 2021 16:54:17 +0100 From: Geert Uytterhoeven To: Tony Lindgren , Russell King , Rajendra Nayak , Paul Walmsley , Michael Turquette , Stephen Boyd , Nicolas Ferre , Alexandre Belloni , Ludovic Desroches , Tero Kristo , Jonathan Cameron , Lars-Peter Clausen , Lorenzo Bianconi , Benoit Parrot , Mauro Carvalho Chehab , Adrian Hunter , Andrew Jeffery , Ulf Hansson , Joel Stanley , Ping-Ke Shih , Kalle Valo , "David S . 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Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui , Jaroslav Kysela , Takashi Iwai Subject: [PATCH/RFC 13/17] pinctl: ti: iodelay: Use bitfield helpers Date: Mon, 22 Nov 2021 16:54:06 +0100 Message-Id: <60257a3c5b567fb5b14d6f9adb770899bce88f7a.1637592133.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 23 Nov 2021 09:20:57 +0100 Cc: alsa-devel@alsa-project.org, Geert Uytterhoeven , linux-aspeed@lists.ozlabs.org, linux-pm@vger.kernel.org, linux-iio@vger.kernel.org, linux-wireless@vger.kernel.org, openbmc@lists.ozlabs.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, netdev@vger.kernel.org, linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Use the field_{get,prep}() helpers, instead of defining a custom function, or open-coding the same operations. Signed-off-by: Geert Uytterhoeven --- Compile-tested only. Marked RFC, as this depends on [PATCH 01/17], but follows a different path to upstream. --- drivers/pinctrl/ti/pinctrl-ti-iodelay.c | 35 +++++++------------------ 1 file changed, 10 insertions(+), 25 deletions(-) diff --git a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c index 4e2382778d38f557..b220dcd9215520db 100644 --- a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c +++ b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c @@ -9,6 +9,7 @@ * warranty of any kind, whether express or implied. */ +#include #include #include #include @@ -155,18 +156,6 @@ struct ti_iodelay_device { struct ti_iodelay_reg_values reg_init_conf_values; }; -/** - * ti_iodelay_extract() - extract bits for a field - * @val: Register value - * @mask: Mask - * - * Return: extracted value which is appropriately shifted - */ -static inline u32 ti_iodelay_extract(u32 val, u32 mask) -{ - return (val & mask) >> __ffs(mask); -} - /** * ti_iodelay_compute_dpe() - Compute equation for delay parameter * @period: Period to use @@ -233,10 +222,10 @@ static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod, } reg_mask = reg->signature_mask; - reg_val = reg->signature_value << __ffs(reg->signature_mask); + reg_val = field_prep(reg->signature_mask, reg->signature_value); reg_mask |= reg->binary_data_coarse_mask; - tmp_val = c_elements << __ffs(reg->binary_data_coarse_mask); + tmp_val = field_prep(reg->binary_data_coarse_mask, c_elements); if (tmp_val & ~reg->binary_data_coarse_mask) { dev_err(dev, "Masking overflow of coarse elements %08x\n", tmp_val); @@ -245,7 +234,7 @@ static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod, reg_val |= tmp_val; reg_mask |= reg->binary_data_fine_mask; - tmp_val = f_elements << __ffs(reg->binary_data_fine_mask); + tmp_val = field_prep(reg->binary_data_fine_mask, f_elements); if (tmp_val & ~reg->binary_data_fine_mask) { dev_err(dev, "Masking overflow of fine elements %08x\n", tmp_val); @@ -260,7 +249,7 @@ static int ti_iodelay_pinconf_set(struct ti_iodelay_device *iod, * impacting iodelay configuration. Use with care! */ reg_mask |= reg->lock_mask; - reg_val |= reg->unlock_val << __ffs(reg->lock_mask); + reg_val |= field_prep(reg->lock_mask, reg->unlock_val); r = regmap_update_bits(iod->regmap, cfg->offset, reg_mask, reg_val); dev_dbg(dev, "Set reg 0x%x Delay(a: %d g: %d), Elements(C=%d F=%d)0x%x\n", @@ -296,16 +285,14 @@ static int ti_iodelay_pinconf_init_dev(struct ti_iodelay_device *iod) r = regmap_read(iod->regmap, reg->reg_refclk_offset, &val); if (r) return r; - ival->ref_clk_period = ti_iodelay_extract(val, reg->refclk_period_mask); + ival->ref_clk_period = field_get(reg->refclk_period_mask, val); dev_dbg(dev, "refclk_period=0x%04x\n", ival->ref_clk_period); r = regmap_read(iod->regmap, reg->reg_coarse_offset, &val); if (r) return r; - ival->coarse_ref_count = - ti_iodelay_extract(val, reg->coarse_ref_count_mask); - ival->coarse_delay_count = - ti_iodelay_extract(val, reg->coarse_delay_count_mask); + ival->coarse_ref_count = field_get(reg->coarse_ref_count_mask, val); + ival->coarse_delay_count = field_get(reg->coarse_delay_count_mask, val); if (!ival->coarse_delay_count) { dev_err(dev, "Invalid Coarse delay count (0) (reg=0x%08x)\n", val); @@ -326,10 +313,8 @@ static int ti_iodelay_pinconf_init_dev(struct ti_iodelay_device *iod) r = regmap_read(iod->regmap, reg->reg_fine_offset, &val); if (r) return r; - ival->fine_ref_count = - ti_iodelay_extract(val, reg->fine_ref_count_mask); - ival->fine_delay_count = - ti_iodelay_extract(val, reg->fine_delay_count_mask); + ival->fine_ref_count = field_get(reg->fine_ref_count_mask, val); + ival->fine_delay_count = field_get(reg->fine_delay_count_mask, val); if (!ival->fine_delay_count) { dev_err(dev, "Invalid Fine delay count (0) (reg=0x%08x)\n", val);