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[4/4] ALSA: hda/intel: Workaround for WALLCLK register for loongson controller

Message ID 608f104f2ad373d60b39f876793c63f265dda8dc.1685501806.git.siyanteng@loongson.cn (mailing list archive)
State Superseded
Headers show
Series Add Loongson HD Audio support | expand

Commit Message

Yanteng Si May 31, 2023, 3:21 a.m. UTC 
On loongson controller, the value of WALLCLK register
is always 0, which is meaningless, so we return directly.

Signed-off-by: Yanteng Si <siyanteng@loongson.cn>
Signed-off-by: Yingkun Meng <mengyingkun@loongson.cn>
---
 sound/pci/hda/hda_intel.c | 3 +++
 1 file changed, 3 insertions(+)
diff mbox series

Patch

diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index f28806b3e308..6df9ec999e88 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -655,6 +655,9 @@  static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
 	unsigned int pos;
 	snd_pcm_uframes_t hwptr, target;
 
+	if (chip->driver_caps & AZX_DCAPS_LOONGSON_WORKAROUND)
+		return 1;
+
 	wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
 	if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
 		return -1;	/* bogus (too early) interrupt */