| Message ID | 6d25d5b36d4b9aeb8655b5e947dad52214e34177.1587693523.git.shengjiu.wang@nxp.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | c38b608504aa1ad8bfa00d85abd61cffad57f27f |
| Headers | show |
| Series | [v2] ASoC: wm8962: set CLOCKING2 as non-volatile register | expand |
On Fri, Apr 24, 2020 at 10:01:38AM +0800, Shengjiu Wang wrote: > Previously CLOCKING2 is set as a volatile register, but cause > issue at suspend & resume, that some bits of CLOCKING2 is not > restored at resume, for example SYSCLK_SRC bits, then the output > clock is wrong. > > The volatile property is caused by CLASSD_CLK_DIV bits, > which are controlled by the chip itself. But the datasheet > claims these are read only and protected by the security key, > and they are not read by the driver at all. > > So it should be safe to change CLOCKING2 to be non-volatile. > > Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> > --- Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Thanks, Charles
On Fri, 24 Apr 2020 10:01:38 +0800, Shengjiu Wang wrote: > Previously CLOCKING2 is set as a volatile register, but cause > issue at suspend & resume, that some bits of CLOCKING2 is not > restored at resume, for example SYSCLK_SRC bits, then the output > clock is wrong. > > The volatile property is caused by CLASSD_CLK_DIV bits, > which are controlled by the chip itself. But the datasheet > claims these are read only and protected by the security key, > and they are not read by the driver at all. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-5.7 Thanks! [1/1] ASoC: wm8962: set CLOCKING2 as non-volatile register commit: c38b608504aa1ad8bfa00d85abd61cffad57f27f All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index d9d59f45833f..0a2cfff44441 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -118,7 +118,7 @@ static const struct reg_default wm8962_reg[] = { { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */ { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */ { 7, 0x000A }, /* R7 - Audio Interface 0 */ - + { 8, 0x01E4 }, /* R8 - Clocking2 */ { 9, 0x0300 }, /* R9 - Audio Interface 1 */ { 10, 0x00C0 }, /* R10 - Left DAC volume */ { 11, 0x00C0 }, /* R11 - Right DAC volume */ @@ -788,7 +788,6 @@ static bool wm8962_volatile_register(struct device *dev, unsigned int reg) { switch (reg) { case WM8962_CLOCKING1: - case WM8962_CLOCKING2: case WM8962_SOFTWARE_RESET: case WM8962_THERMAL_SHUTDOWN_STATUS: case WM8962_ADDITIONAL_CONTROL_4:
Previously CLOCKING2 is set as a volatile register, but cause issue at suspend & resume, that some bits of CLOCKING2 is not restored at resume, for example SYSCLK_SRC bits, then the output clock is wrong. The volatile property is caused by CLASSD_CLK_DIV bits, which are controlled by the chip itself. But the datasheet claims these are read only and protected by the security key, and they are not read by the driver at all. So it should be safe to change CLOCKING2 to be non-volatile. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> --- Changes in v2: - Change according to Charles's suggestion to use non-volatile sound/soc/codecs/wm8962.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)