From patchwork Fri Jul 3 09:13:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zidan Wang X-Patchwork-Id: 6713651 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 69306C05AC for ; Fri, 3 Jul 2015 09:12:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 19065206E2 for ; Fri, 3 Jul 2015 09:12:32 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 3075220429 for ; Fri, 3 Jul 2015 09:12:30 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id E63AE261A64; Fri, 3 Jul 2015 11:12:28 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,NO_DNS_FOR_FROM, UNPARSEABLE_RELAY autolearn=no version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id 6A72A260484; Fri, 3 Jul 2015 11:12:18 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id E90A1260527; Fri, 3 Jul 2015 11:12:14 +0200 (CEST) Received: from na01-bl2-obe.outbound.protection.outlook.com (mail-bl2on0137.outbound.protection.outlook.com [65.55.169.137]) by alsa0.perex.cz (Postfix) with ESMTP id ED147260476 for ; Fri, 3 Jul 2015 11:12:06 +0200 (CEST) Received: from DM2PR03CA0045.namprd03.prod.outlook.com (10.141.96.44) by CY1PR0301MB1258.namprd03.prod.outlook.com (10.161.212.156) with Microsoft SMTP Server (TLS) id 15.1.195.15; Fri, 3 Jul 2015 09:12:04 +0000 Received: from BL2FFO11FD021.protection.gbl (2a01:111:f400:7c09::181) by DM2PR03CA0045.outlook.office365.com (2a01:111:e400:2428::44) with Microsoft SMTP Server (TLS) id 15.1.201.16 via Frontend Transport; Fri, 3 Jul 2015 09:12:04 +0000 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BL2FFO11FD021.mail.protection.outlook.com (10.173.161.100) with Microsoft SMTP Server (TLS) id 15.1.201.10 via Frontend Transport; Fri, 3 Jul 2015 09:12:04 +0000 Received: from b50113.ap.freescale.net (b50113.ap.freescale.net [10.192.241.89]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t639BxmC013920; Fri, 3 Jul 2015 02:12:00 -0700 From: Zidan Wang To: Date: Fri, 3 Jul 2015 17:13:42 +0800 Message-ID: X-Mailer: git-send-email 1.9.1 X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BL2FFO11FD021; 1:S9PA+eFUvoFnhcjvdD0MQmgsFnDs4yrQP8KvwomGXtDNErZJpNfVgam4ZNUytFXcrKnsMQIVQQs+dmxmiRO7vvIVmwqr0eV6duL9T+e7oi1dNfffetWbFe1WdBTDijm5x+K+6uGrVijnOSM1clCHg12k0UBaJq72TtOTY0N9pYKWqWeDqJy7lXgGXyKXS3HmuEI3JjUPWh3EZuV7ei9lbbR4EA6N6IzoYZp5xujEaxLALhdlqn/PBtbPZwGN6J1hoR0okH20Q/dx8BOZ5mby99JAKafwfBqTaXZ/YKLf/lzFadMDUjCIHENS7r0EIZtGCY/UtUbAW29RDZbI72X5yHgFowC3t365+Nj1GjWoYNVz/ZvI3IRZ4NYcTRvxAevS X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(2980300002)(1060300003)(339900001)(199003)(189002)(48376002)(50466002)(118296001)(36756003)(4290100001)(92566002)(46102003)(106466001)(19580395003)(19580405001)(86362001)(110136002)(5001960100002)(107886002)(50986999)(50226001)(6806004)(110436001)(2351001)(229853001)(104016003)(85426001)(87936001)(62966003)(77096005)(33646002)(47776003)(105606002)(77156002)(4001430100001); DIR:OUT; SFP:1102; SCL:1; SRVR:CY1PR0301MB1258; H:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:sfv; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB1258; 2:WSGUgCUc3N5DKJeHt+ZtEns0gv4JbDYZ5xi3IeyWfEFg9wMmfJfTjQ4TavrM1O0n; 3:WK9UwojB9M3rYUnb0vCOKLxVCLTsMBL4ouG6Ez6OcW28Q/N2p112UAAeVkndCJxWuDhvGpJblCZ8NQLLIFIiM+4yiDixWwpwJ2UAP/apIlzwbxmEtP4WWga1qrEwTF8JgIYuGEvaKJqHrVChhrgzvLfG1vJ/cv164JO+T+XumjrdqiiI3WGk2kWR2VBmUB7svIqY25xmoVPuRTfufOQiEfrAxZRgpy9GWXvwRzv0U9c=; 20:d1uImZem0MwW2DbXLJ5tOXka6xrrSFXSLtURsq/PCnvX+TxRhDbWCP8Sdxb79pRi1VuSyoRaBcZF4SYDdrU9EBpTp8LpiWFQ1rqiPJDmi0UYXy8NB0t8RfPplsLcH7oH2/7hy5kC8ikLOx1JN90bjaf8pLzz7HVgvW2P/0AozgPwERchAGzkvK2tPMr1+18mTxfWM1O4Gq6ybhxCO4xe6hMe5/37LlZLpOKumpANe6feYmCvdPQ6SvIC3RcQcPgYX/453yRxi0kN7Jnc6S5rhRU1cRLQK83uwo5scPtYjp/Tyr/38+SnCGLgFlQvo3Zs8uZ3EwoL0LpkBK5ykked5+dn3AQgdOhiUr7Kcbnc11Q= X-Microsoft-Antispam: UriScan:;BCL:1;PCL:0;RULEID:;SRVR:CY1PR0301MB1258; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:1; PCL:0; RULEID:(601004)(1201001)(5005006)(3002001); SRVR:CY1PR0301MB1258; BCL:1; PCL:0; RULEID:; SRVR:CY1PR0301MB1258; X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB1258; 4:3SdC3u1Ntxi3gqlGHw1ZBBMxqtOQUCnyerstfgdXFioovNBCsr7c36OZkXxMy9e1osbhiszGyF2GcNTc/5iuRlcgZUMb6Y7cWjSkIUqDQG5wvjtpOUWaNP9IcjApsT4fWo8mhOEio1DlTfRMqb1SIfYgqQJAilFm5nHwZc2cbiQ4be1FIdUbUtrxXLaiYAIiygOFGK30hKYXyAZ/puAEZjGABMYd/Iw8QEyAj41pgIDGlZrGIAm5xlIvRHEaBi/oKzdoEqbqmQ8dLsOvv5o9ZJv1s4oHkgTXAjKzOQl5J6TVeUg+sk17cnQvap2lkYzj X-Forefront-PRVS: 0626C21B10 X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB1258; 23:GnRjqHCwpcC/r0pviQqfiuUFpbvU3/CqTw0uFRrhH5YJGqn/Hj9ZXLLSxEgWh2No6We+KSCBiWAl+dCGRGH2Yy24oVfP2YrO+PtataCDabJ41DTey8XfN8ATpnGCsflRtM1q+JiMOiViZGDaU2NfLgIXogPJi/z4atYLNBCBsFaiwK1NudcoLBuM+02KY1z1WuRWNHa4gKOm3NtmuWTiXf4Eo6yay47Y3tgFMnTihLpuZUcsD5/72YlofmV3piREtv/S1OXEX8fSc38RoH8OdDWWxHPLpMTMX0sp7ge9XXGCdubvwqBkrECnja4WOQzo+7Iz/KFl/WLM08eMPDcdOo9po2hteqQDDtg12R17SQ+yk5y1KQ577wrmv+QAmBJmyqt25uKWLyDemewnLkqdBKvP0LpC7sSVDKVtci1IyTcHfL4ro+Dbl00gYboKhutlt4kY1oOOS7QZwoRv62OcpFiDz0k0A3dtl8Dz7SApLGaG9whTDofKU/KQB/6ATHbrbuZPf+p9XkxJMqkYtQSqf/7SL+HRX6N7mIT78ZD+Rhw88tCcxv6mPnLTBV4fiusDtPtMQT8nCpRakkKoJU1bGyebv4fZ1OSR5PJwLbaDQtNavBvony3AK0Px4v9gyo214glvybMPwCtSIWzVWHY4aB9bDvfNYPSPixpCpSzy2q503AiEmWh4w5iblTdZWMahU2J8jHQvw+KJzA7Sa87Pm/Om9n2pnqhnSez9s3bbFuXsFlgsDfzkGpdJ4aroxQP8ua2UYIVODqgUk77CI5tPxVhTltwCjB97GTg6gTOcAIx0Tq882RemElF0gW57iJ9QQbpOZ4ekyRsmIkf0fx6wfuiNkHqPX4dYpsT4QEnNViVYbC9jMi+9q3GEziOHIf16dyKA+oAmlnv7pKwymSkp6AIyZ5qlgKrE6aDvuojEHEGX4U1RUT8czeXhx16F51zt X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB1258; 5:4LEJJq3MQpf2jeyudZX2C6OSk5ol9FMpqOv/MZzZzDwCNmZm6nygBTLL2pZWRbW1k35JS2ReFJOJrLfvB64n5d9zHZV7roy5LEhA3XafRm0iiPxCx1R+ZRu2aRdKnmgRUTLnKG2JB6wWtft/wMCWwQ==; 24:StbRnZeHKE6lqVZoWuYHStVfHe58AdeCfdkth5OwNIkrm3iFEfQukDvkGq2uexptB0rCuYr2TqdNb6fEHhQc1cQRdUnp3/y35QEq9CDeO+c=; 20:BCEngxpWtvDgOnu3VAg12ZUEteGXX68JgcpxM+XqgQmcKXP6cm3aqCqcy1zwqS4524dfMWnX43omhSmttXiYWQ== X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jul 2015 09:12:04.1410 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0301MB1258 Cc: alsa-devel@alsa-project.org, lars@metafoo.de, Zidan Wang , tiwai@suse.de, patches@opensource.wolfsonmicro.com, linux-kernel@vger.kernel.org, ckeepax@opensource.wolfsonmicro.com Subject: [alsa-devel] [PATCH v2] ASoC: wm8960: update pll and clock setting function X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP Add sysclk auto mode. When it's sysclk auto mode, if the MCLK is available for clock configure, using MCLK to provide sysclk directly, otherwise, search a available pll out frequcncy and set pll. TX and RX share the same sysclk and bclk divider register, and have different DAC/ADC divier register. When playback and capture simultaneously, the second stream should not set pll, should not change the sysclk and bclk, just need set DAC/ADC divider to support different TX and RX sample rate. Signed-off-by: Zidan Wang --- sound/soc/codecs/wm8960.c | 256 ++++++++++++++++++++++++++++++++++++++-------- sound/soc/codecs/wm8960.h | 1 + 2 files changed, 214 insertions(+), 43 deletions(-) diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c index 94c5c46..e170bdf 100644 --- a/sound/soc/codecs/wm8960.c +++ b/sound/soc/codecs/wm8960.c @@ -48,6 +48,9 @@ #define WM8960_DISOP 0x40 #define WM8960_DRES_MASK 0x30 +static bool is_pll_freq_available(unsigned int source, unsigned int target); +static int wm8960_set_pll(struct snd_soc_dai *codec_dai, + unsigned int freq_in, unsigned int freq_out); /* * wm8960 register cache * We can't read the WM8960 register space when we are @@ -126,9 +129,12 @@ struct wm8960_priv { struct snd_soc_dapm_widget *rout1; struct snd_soc_dapm_widget *out3; bool deemph; - int playback_fs; - int bclk; int sysclk; + int clk_id; + int freq_in; + int fs[2]; + int dac_div[2]; + bool is_stream_in_use[2]; struct wm8960_data pdata; }; @@ -164,8 +170,8 @@ static int wm8960_set_deemph(struct snd_soc_codec *codec) if (wm8960->deemph) { best = 1; for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { - if (abs(deemph_settings[i] - wm8960->playback_fs) < - abs(deemph_settings[best] - wm8960->playback_fs)) + if (abs(deemph_settings[i] - wm8960->fs[1]) < + abs(deemph_settings[best] - wm8960->fs[1])) best = i; } @@ -565,6 +571,9 @@ static struct { { 8000, 5 }, }; +/* -1 for reserved value */ +static const int sysclk_divs[] = { 1, -1, 2, -1 }; + /* Multiply 256 for internal 256 div */ static const int dac_divs[] = { 256, 384, 512, 768, 1024, 1408, 1536 }; @@ -574,61 +583,166 @@ static const int bclk_divs[] = { 120, 160, 220, 240, 320, 320, 320 }; -static void wm8960_configure_clocking(struct snd_soc_codec *codec, - bool tx, int lrclk) +static int wm8960_configure_clocking(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { + struct snd_soc_codec *codec = dai->codec; struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); + unsigned int sample_rate = params_rate(params); + unsigned int channels = params_channels(params); + unsigned int sysclk, bclk, freq_out, freq_in; + bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; u16 iface1 = snd_soc_read(codec, WM8960_IFACE1); u16 iface2 = snd_soc_read(codec, WM8960_IFACE2); - u32 sysclk; - int i, j; + int i, j, k; if (!(iface1 & (1<<6))) { dev_dbg(codec->dev, "Codec is slave mode, no need to configure clock\n"); - return; + return 0; + } + + /* + * playback and capture using the same registers of bclk and sysclk + * div, and different registers for dac/adc div. If playback and capture + * simultaneously, the second should not set pll, should not change + * the sysclk and bclk, only dac/adc div can be set to support different + * frame clock. + */ + if (wm8960->is_stream_in_use[!tx]) { + /* + * If ADCLRC configure as GPIO pin, DACLRC pin is used as a + * frame clock for ADCs and DACs. + */ + if (iface2 & (1 << 6)) { + snd_soc_update_bits(codec, WM8960_CLOCK1, + 0x7 << 3, wm8960->dac_div[!tx] << 3); + return 0; + } + + /* + * If the different TX and RX sample rate can be support, + * setting corresponding DAC or ADC divider. + */ + for (i = 0; i < ARRAY_SIZE(dac_divs); ++i) { + if (wm8960->fs[!tx] * dac_divs[wm8960->dac_div[!tx]] + == wm8960->fs[tx] * dac_divs[i]) { + if (tx) + snd_soc_update_bits(codec, + WM8960_CLOCK1, + 0x7 << 3, dac_divs[i] << 3); + else + snd_soc_update_bits(codec, + WM8960_CLOCK1, + 0x7 << 6, dac_divs[i] << 6); + wm8960->dac_div[tx] = dac_divs[i]; + return 0; + } + } + if (i == ARRAY_SIZE(dac_divs)) { + dev_err(codec->dev, + "can't support TX=%d RX=%d\n simultaneously", + wm8960->fs[1], wm8960->fs[0]); + return -EINVAL; + } + } + + if (wm8960->clk_id != WM8960_SYSCLK_MCLK && !wm8960->freq_in) { + dev_err(codec->dev, "No MCLK configured\n"); + return -EINVAL; } - if (!wm8960->sysclk) { - dev_dbg(codec->dev, "No SYSCLK configured\n"); - return; + freq_in = wm8960->freq_in; + + bclk = snd_soc_params_to_bclk(params); + if (channels == 1) + bclk *= 2; + + /* + * If it's sysclk auto mode, check if the MCLK can provide sysclk or + * not. If MCLK can provide sysclk, using MCLK to provide sysclk + * directly. Otherwise, auto select a available pll out frequency + * and set PLL. + */ + if (wm8960->clk_id == WM8960_SYSCLK_AUTO) { + /* disable the PLL and using MCLK to provide sysclk */ + wm8960_set_pll(dai, 0, 0); + freq_out = freq_in; + } else if (wm8960->sysclk) + freq_out = wm8960->sysclk; + else { + dev_err(codec->dev, "No SYSCLK configured\n"); + return -EINVAL; } - if (!wm8960->bclk || !lrclk) { - dev_dbg(codec->dev, "No audio clocks configured\n"); - return; + /* check if the sysclk frequency is available. */ + for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) { + if (sysclk_divs[i] == -1) + continue; + sysclk = freq_out / sysclk_divs[i]; + for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) { + if (sysclk == dac_divs[j] * sample_rate) { + for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) + if (sysclk == bclk * bclk_divs[k] / 10) + break; + if (k != ARRAY_SIZE(bclk_divs)) + break; + } + } + if (j != ARRAY_SIZE(dac_divs)) + break; } - for (i = 0; i < ARRAY_SIZE(dac_divs); ++i) { - if (wm8960->sysclk == lrclk * dac_divs[i]) { - for (j = 0; j < ARRAY_SIZE(bclk_divs); ++j) { - sysclk = wm8960->bclk * bclk_divs[j] / 10; - if (wm8960->sysclk == sysclk) + if (i != ARRAY_SIZE(sysclk_divs)) + goto configure_clock; + else if (wm8960->clk_id != WM8960_SYSCLK_AUTO) { + dev_err(codec->dev, "failed to configure clock\n"); + return -EINVAL; + } + /* get a available pll out frequency and set pll */ + for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) { + if (sysclk_divs[i] == -1) + continue; + for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) { + sysclk = sample_rate * dac_divs[j]; + freq_out = sysclk * sysclk_divs[i]; + + for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) { + if (sysclk == bclk * bclk_divs[k] / 10 && + is_pll_freq_available(freq_in, freq_out)) { + wm8960_set_pll(dai, freq_in, freq_out); break; + } else + continue; } - if(j != ARRAY_SIZE(bclk_divs)) + if (k != ARRAY_SIZE(bclk_divs)) break; } + if (j != ARRAY_SIZE(dac_divs)) + break; } - if (i == ARRAY_SIZE(dac_divs)) { - dev_err(codec->dev, "Unsupported sysclk %d\n", wm8960->sysclk); - return; + if (i == ARRAY_SIZE(sysclk_divs)) { + dev_err(codec->dev, "failed to configure clock\n"); + return -EINVAL; } - /* - * configure frame clock. If ADCLRC configure as GPIO pin, DACLRC - * pin is used as a frame clock for ADCs and DACs. - */ - if (iface2 & (1<<6)) - snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, i << 3); +configure_clock: + snd_soc_update_bits(codec, WM8960_CLOCK1, 3 << 1, i << 1); + + if (iface2 & (1 << 6)) + snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, j << 3); else if (tx) - snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, i << 3); + snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, j << 3); else if (!tx) - snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 6, i << 6); + snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 6, j << 6); /* configure bit clock */ - snd_soc_update_bits(codec, WM8960_CLOCK2, 0xf, j); + snd_soc_update_bits(codec, WM8960_CLOCK2, 0xf, k); + + wm8960->dac_div[tx] = j; + + return 0; } static int wm8960_hw_params(struct snd_pcm_substream *substream, @@ -641,10 +755,6 @@ static int wm8960_hw_params(struct snd_pcm_substream *substream, bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; int i; - wm8960->bclk = snd_soc_params_to_bclk(params); - if (params_channels(params) == 1) - wm8960->bclk *= 2; - /* bit size */ switch (params_width(params)) { case 16: @@ -667,11 +777,11 @@ static int wm8960_hw_params(struct snd_pcm_substream *substream, return -EINVAL; } + wm8960->fs[tx] = params_rate(params); /* Update filters for the new rate */ - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - wm8960->playback_fs = params_rate(params); + if (tx) wm8960_set_deemph(codec); - } else { + else { for (i = 0; i < ARRAY_SIZE(alc_rates); i++) if (alc_rates[i].rate == params_rate(params)) snd_soc_update_bits(codec, @@ -682,7 +792,27 @@ static int wm8960_hw_params(struct snd_pcm_substream *substream, /* set iface */ snd_soc_write(codec, WM8960_IFACE1, iface); - wm8960_configure_clocking(codec, tx, params_rate(params)); + wm8960->is_stream_in_use[tx] = true; + + return wm8960_configure_clocking(substream, params, dai); +} + +static int wm8960_hw_free(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); + u16 clock1 = snd_soc_read(codec, WM8960_CLOCK1); + bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; + + wm8960->is_stream_in_use[tx] = false; + /* + * If it's sysclk auto mode, no stream in use, and the pll is enabled, + * disable the pll + */ + if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (clock1 & 0x1) && + !wm8960->is_stream_in_use[!tx]) + wm8960_set_pll(dai, 0, 0); return 0; } @@ -892,6 +1022,28 @@ struct _pll_div { u32 k:24; }; +static bool is_pll_freq_available(unsigned int source, unsigned int target) +{ + unsigned int Ndiv; + + if (source == 0 || target == 0) + return false; + + /* Scale up target to PLL operating frequency */ + target *= 4; + Ndiv = target / source; + + if (Ndiv < 6) { + source >>= 1; + Ndiv = target / source; + } + + if ((Ndiv < 6) || (Ndiv > 12)) + return false; + + return true; +} + /* The size in bits of the pll divide multiplied by 10 * to allow rounding later */ #define FIXED_PLL_SIZE ((1 << 24) * 10) @@ -943,8 +1095,8 @@ static int pll_factors(unsigned int source, unsigned int target, return 0; } -static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, - int source, unsigned int freq_in, unsigned int freq_out) +static int wm8960_set_pll(struct snd_soc_dai *codec_dai, + unsigned int freq_in, unsigned int freq_out) { struct snd_soc_codec *codec = codec_dai->codec; u16 reg; @@ -986,6 +1138,20 @@ static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, return 0; } +static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, + int source, unsigned int freq_in, unsigned int freq_out) +{ + struct snd_soc_codec *codec = codec_dai->codec; + struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); + + wm8960->freq_in = freq_in; + + if (wm8960->clk_id == WM8960_SYSCLK_AUTO) + return 0; + + return wm8960_set_pll(codec_dai, freq_in, freq_out); +} + static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div) { @@ -1043,11 +1209,14 @@ static int wm8960_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, snd_soc_update_bits(codec, WM8960_CLOCK1, 0x1, WM8960_SYSCLK_PLL); break; + case WM8960_SYSCLK_AUTO: + break; default: return -EINVAL; } wm8960->sysclk = freq; + wm8960->clk_id = clk_id; return 0; } @@ -1060,6 +1229,7 @@ static int wm8960_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, static const struct snd_soc_dai_ops wm8960_dai_ops = { .hw_params = wm8960_hw_params, + .hw_free = wm8960_hw_free, .digital_mute = wm8960_mute, .set_fmt = wm8960_set_dai_fmt, .set_clkdiv = wm8960_set_dai_clkdiv, diff --git a/sound/soc/codecs/wm8960.h b/sound/soc/codecs/wm8960.h index 2d8163d..ab3220d 100644 --- a/sound/soc/codecs/wm8960.h +++ b/sound/soc/codecs/wm8960.h @@ -82,6 +82,7 @@ #define WM8960_SYSCLK_MCLK (0 << 0) #define WM8960_SYSCLK_PLL (1 << 0) +#define WM8960_SYSCLK_AUTO (2 << 0) #define WM8960_DAC_DIV_1 (0 << 3) #define WM8960_DAC_DIV_1_5 (1 << 3)