From patchwork Sun Dec 2 21:23:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mesih Kilinc X-Patchwork-Id: 10709359 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10A1715A6 for ; Mon, 3 Dec 2018 11:48:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F3EA42B45E for ; Mon, 3 Dec 2018 11:48:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E5AC32B459; Mon, 3 Dec 2018 11:48:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8DE982B459 for ; Mon, 3 Dec 2018 11:48:18 +0000 (UTC) Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 7ACF5267AED; Mon, 3 Dec 2018 12:47:08 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 5908D267A76; Sun, 2 Dec 2018 22:23:40 +0100 (CET) Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by alsa0.perex.cz (Postfix) with ESMTP id BF61A26784E for ; Sun, 2 Dec 2018 22:23:37 +0100 (CET) Received: by mail-wm1-f65.google.com with SMTP id z18so3788339wmc.4 for ; Sun, 02 Dec 2018 13:23:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7yyznife34qc5hftjhmlPj2tKij05JG3MZXRdWCCZxQ=; b=hSodrmB7WNhYM3hepxJhG1wSZHTijT3Gbx2FV/H4g9443iGNczH6BCaRngFkTJU7UH mKfOg+nl7tbkbvcjQ6UeeH5D28YFZWezCy7llRmdQ+WPSGRb07k9dxB/iS++QO9GpeHY pS3sJOgnEOWiNFyYMEtI6oBBVRiu9tWGmppSKrGsky+qIXcGtVVdyzFMUYed6qNYR6vG NbA5DGKB/MEEp7zgxbyVbn946gsswRWmBwbyFuMdxXuC1gdrAJnkAG605aDeHzVUhwvw j31DXqi/8GlfrUNmMFLo6XoM4ofPM4O5Tc0Rg0epWvwJ0z0epKeVs94OGnf/kNSmAp5A TNJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7yyznife34qc5hftjhmlPj2tKij05JG3MZXRdWCCZxQ=; b=p90XFJmlOMk6lozuhmwcUZkCrZKjQErBIcZK0QCt3L8ynHxCECOi2fJjPhhfxxH/cN 40Cdd1iRz1dhL6siMppUG8lW6uGuhecdJ6YpuDbEeiqW2lto+vCeiMPPjBGCXvl1PlaL 6iuwlG9usF4r4UPFyeYd6wZOx8Pnfaj80eK1JOUyJY16Si+IZzi1MM+q66TzoqZQGMYR md/RAVFFJfEqk2W1wez2Ca62tOf1l7Wfn3PRSZD2xibLxxJ9O7t04x9otgVWLazEdmsc 9xRN0F1UE7dn+aVH5I6BzpQ6jsuCfcRIYshzg1tlUYShuF0t9idQw8Rk4I+tor2lePFf 66Eg== X-Gm-Message-State: AA+aEWbm5WFx72sZER0HnQW0qB121P1EXWNmWEJS8OG0olXIzP5ZFjC2 Cu6EEjeiBlMzWtQHnCl4j9DwU/K2T30= X-Google-Smtp-Source: AFSGD/V3b5skn+Nmeueq22w0VIu9mzLvFEgabPR8VlTqgRZ/sfDWX1UAvvzx1vlUrXlHhUCpW6PWDg== X-Received: by 2002:a1c:1903:: with SMTP id 3-v6mr5716302wmz.141.1543785817487; Sun, 02 Dec 2018 13:23:37 -0800 (PST) Received: from ThinkPad.home ([185.219.177.152]) by smtp.gmail.com with ESMTPSA id d2sm9551043wrs.97.2018.12.02.13.23.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 02 Dec 2018 13:23:37 -0800 (PST) From: Mesih Kilinc To: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, linux-sunxi@googlegroups.com Date: Mon, 3 Dec 2018 00:23:11 +0300 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: X-Mailman-Approved-At: Mon, 03 Dec 2018 12:46:49 +0100 Cc: Mark Rutland , Mesih Kilinc , Mark Brown , Takashi Iwai , Chen-Yu Tsai , Liam Girdwood , Maxime Ripard , Vinod Koul , Rob Herring Subject: [alsa-devel] [RFC PATCH 04/10] dma-engine: sun4i: Add support for Allwinner suniv F1C100s X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP DMA of Allwinner suniv F1C100s is similar to sun4i. It has 4 NDMA, 4 DDMA channels and endpoints are different. Also F1C100s has reset bit for DMA in CCU. Add support for it. Signed-off-by: Mesih Kilinc --- drivers/dma/Kconfig | 4 ++-- drivers/dma/sun4i-dma.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 2 deletions(-) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index de511db..f8a65d2 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -163,8 +163,8 @@ config DMA_SA11X0 config DMA_SUN4I tristate "Allwinner A10 DMA SoCs support" - depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I - default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNIV + default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNIV) select DMA_ENGINE select DMA_VIRTUAL_CHANNELS help diff --git a/drivers/dma/sun4i-dma.c b/drivers/dma/sun4i-dma.c index d267ff9..c0452c9 100644 --- a/drivers/dma/sun4i-dma.c +++ b/drivers/dma/sun4i-dma.c @@ -36,7 +36,11 @@ #define SUN4I_DMA_CFG_SRC_ADDR_MODE(mode) ((mode) << 5) #define SUN4I_DMA_CFG_SRC_DRQ_TYPE(type) (type) +#define SUNIV_DMA_CFG_DST_DATA_WIDTH(width) ((width) << 24) +#define SUNIV_DMA_CFG_SRC_DATA_WIDTH(width) ((width) << 8) + #define SUN4I_MAX_BURST 8 +#define SUNIV_MAX_BURST 4 /** Normal DMA register values **/ @@ -44,6 +48,9 @@ #define SUN4I_NDMA_DRQ_TYPE_SDRAM 0x16 #define SUN4I_NDMA_DRQ_TYPE_LIMIT (0x1F + 1) +#define SUNIV_NDMA_DRQ_TYPE_SDRAM 0x11 +#define SUNIV_NDMA_DRQ_TYPE_LIMIT (0x17 + 1) + /** Normal DMA register layout **/ /* Dedicated DMA source/destination address mode values */ @@ -57,6 +64,9 @@ #define SUN4I_NDMA_CFG_BYTE_COUNT_MODE_REMAIN BIT(15) #define SUN4I_NDMA_CFG_SRC_NON_SECURE BIT(6) +#define SUNIV_NDMA_CFG_CONT_MODE BIT(29) +#define SUNIV_NDMA_CFG_WAIT_STATE(n) ((n) << 26) + /** Dedicated DMA register values **/ /* Dedicated DMA source/destination address mode values */ @@ -69,6 +79,9 @@ #define SUN4I_DDMA_DRQ_TYPE_SDRAM 0x1 #define SUN4I_DDMA_DRQ_TYPE_LIMIT (0x1F + 1) +#define SUNIV_DDMA_DRQ_TYPE_SDRAM 0x1 +#define SUNIV_DDMA_DRQ_TYPE_LIMIT (0x9 + 1) + /** Dedicated DMA register layout **/ /* Dedicated DMA configuration register layout */ @@ -122,6 +135,11 @@ #define SUN4I_DMA_NR_MAX_VCHANS \ (SUN4I_NDMA_NR_MAX_VCHANS + SUN4I_DDMA_NR_MAX_VCHANS) +#define SUNIV_NDMA_NR_MAX_CHANNELS 4 +#define SUNIV_DDMA_NR_MAX_CHANNELS 4 +#define SUNIV_NDMA_NR_MAX_VCHANS (24 * 2 - 1) +#define SUNIV_DDMA_NR_MAX_VCHANS 10 + /* This set of SUN4I_DDMA timing parameters were found experimentally while * working with the SPI driver and seem to make it behave correctly */ #define SUN4I_DDMA_MAGIC_SPI_PARAMETERS \ @@ -236,6 +254,16 @@ static void set_src_data_width_a10(u32 *p_cfg, s8 data_width) *p_cfg |= SUN4I_DMA_CFG_SRC_DATA_WIDTH(data_width); } +static void set_dst_data_width_f1c100s(u32 *p_cfg, s8 data_width) +{ + *p_cfg |= SUNIV_DMA_CFG_DST_DATA_WIDTH(data_width); +} + +static void set_src_data_width_f1c100s(u32 *p_cfg, s8 data_width) +{ + *p_cfg |= SUNIV_DMA_CFG_SRC_DATA_WIDTH(data_width); +} + static int convert_burst_a10(u32 maxburst) { if (maxburst > 8) @@ -245,6 +273,15 @@ static int convert_burst_a10(u32 maxburst) return (maxburst >> 2); } +static int convert_burst_f1c100s(u32 maxburst) +{ + if (maxburst > 4) + return -EINVAL; + + /* 1 -> 0, 4 -> 1 */ + return (maxburst >> 2); +} + static int convert_buswidth(enum dma_slave_buswidth addr_width) { if (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES) @@ -1364,8 +1401,31 @@ static struct sun4i_dma_config sun4i_a10_dma_cfg = { .has_reset = false, }; +static struct sun4i_dma_config suniv_f1c100s_dma_cfg = { + .ndma_nr_max_channels = SUNIV_NDMA_NR_MAX_CHANNELS, + .ndma_nr_max_vchans = SUNIV_NDMA_NR_MAX_VCHANS, + + .ddma_nr_max_channels = SUNIV_DDMA_NR_MAX_CHANNELS, + .ddma_nr_max_vchans = SUNIV_DDMA_NR_MAX_VCHANS, + + .dma_nr_max_channels = SUNIV_NDMA_NR_MAX_CHANNELS + + SUNIV_DDMA_NR_MAX_CHANNELS, + + .set_dst_data_width = set_dst_data_width_f1c100s, + .set_src_data_width = set_src_data_width_f1c100s, + .convert_burst = convert_burst_f1c100s, + + .ndma_drq_sdram = SUNIV_NDMA_DRQ_TYPE_SDRAM, + .ddma_drq_sdram = SUNIV_DDMA_DRQ_TYPE_SDRAM, + + .max_burst = SUNIV_MAX_BURST, + .has_reset = true, +}; + static const struct of_device_id sun4i_dma_match[] = { { .compatible = "allwinner,sun4i-a10-dma", .data = &sun4i_a10_dma_cfg }, + { .compatible = "allwinner,suniv-f1c100s-dma", + .data = &suniv_f1c100s_dma_cfg }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, sun4i_dma_match);