From patchwork Tue Sep 9 09:18:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shengjiu Wang X-Patchwork-Id: 4867081 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1DD6D9F3EC for ; Tue, 9 Sep 2014 09:19:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D17CA20145 for ; Tue, 9 Sep 2014 09:19:06 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 18E4820035 for ; Tue, 9 Sep 2014 09:19:05 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 7EE18265083; Tue, 9 Sep 2014 11:19:02 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id B82F1264F19; Tue, 9 Sep 2014 11:18:52 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 7EC07264F1E; Tue, 9 Sep 2014 11:18:49 +0200 (CEST) Received: from na01-bl2-obe.outbound.protection.outlook.com (mail-bl2on0146.outbound.protection.outlook.com [65.55.169.146]) by alsa0.perex.cz (Postfix) with ESMTP id 35C3326262A for ; Tue, 9 Sep 2014 11:18:39 +0200 (CEST) Received: from BN3PR0301CA0046.namprd03.prod.outlook.com (25.160.152.142) by DM2PR0301MB0623.namprd03.prod.outlook.com (25.160.95.27) with Microsoft SMTP Server (TLS) id 15.0.1024.12; Tue, 9 Sep 2014 09:18:34 +0000 Received: from BN1AFFO11FD014.protection.gbl (2a01:111:f400:7c10::161) by BN3PR0301CA0046.outlook.office365.com (2a01:111:e400:401e::14) with Microsoft SMTP Server (TLS) id 15.0.1024.12 via Frontend Transport; Tue, 9 Sep 2014 09:18:34 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1AFFO11FD014.mail.protection.outlook.com (10.58.52.74) with Microsoft SMTP Server (TLS) id 15.0.1019.14 via Frontend Transport; Tue, 9 Sep 2014 09:18:33 +0000 Received: from audiosh1.ap.freescale.net (audiosh1.ap.freescale.net [10.192.241.205]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s899IHYB009609; Tue, 9 Sep 2014 02:18:22 -0700 From: Shengjiu Wang To: , , , , , , Date: Tue, 9 Sep 2014 17:18:07 +0800 Message-ID: X-Mailer: git-send-email 1.7.9.5 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019018)(6009001)(189002)(199003)(83072002)(102836001)(26826002)(85852003)(84676001)(77156001)(87936001)(50226001)(104166001)(229853001)(62966002)(21056001)(77982001)(88136002)(85306004)(33646002)(118296001)(4396001)(90102001)(89996001)(79102001)(104016003)(87286001)(46102001)(93916002)(575784001)(86362001)(99396002)(50986999)(95666004)(105606002)(92726001)(92566001)(106466001)(19580395003)(19580405001)(44976005)(83322001)(68736004)(6806004)(74502001)(76482001)(74662001)(107046002)(36756003)(2201001)(31966008)(64706001)(20776003)(50466002)(47776003)(81542001)(97736003)(81342001)(48376002)(80022001)(2101003); DIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR0301MB0623; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 0329B15C8A Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=shengjiu.wang@freescale.com; X-OriginatorOrg: freescale.com Cc: alsa-devel@alsa-project.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [alsa-devel] [PATCH V1] ASoC: fsl_ssi: refine ipg clock usage in this module X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP Move the ipg clock enable and disable operation to startup and shutdown, that is only enable ipg clock when ssi is working. we don't need to enable ipg clock in probe. Another register accessing need the ipg clock, so use devm_regmap_init_mmio_clk instead of devm_regmap_init_mmio. Signed-off-by: Shengjiu Wang --- sound/soc/fsl/fsl_ssi.c | 38 +++++++++++++++++++++++++++----------- 1 file changed, 27 insertions(+), 11 deletions(-) diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index 2fc3e66..d32d0f5 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -531,6 +531,9 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream, struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); + if (ssi_private->soc->imx) + clk_prepare_enable(ssi_private->clk); + /* When using dual fifo mode, it is safer to ensure an even period * size. If appearing to an odd number while DMA always starts its * task from fifo0, fifo1 would be neglected at the end of each @@ -544,6 +547,22 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream, } /** + * fsl_ssi_shutdown: shutdown the SSI + * + */ +static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct fsl_ssi_private *ssi_private = + snd_soc_dai_get_drvdata(rtd->cpu_dai); + + if (ssi_private->soc->imx) + clk_disable_unprepare(ssi_private->clk); + +} + +/** * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock * * Note: This function can be only called when using SSI as DAI master @@ -1043,6 +1062,7 @@ static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { .startup = fsl_ssi_startup, + .shutdown = fsl_ssi_shutdown, .hw_params = fsl_ssi_hw_params, .hw_free = fsl_ssi_hw_free, .set_fmt = fsl_ssi_set_dai_fmt, @@ -1168,16 +1188,10 @@ static int fsl_ssi_imx_probe(struct platform_device *pdev, u32 dmas[4]; int ret; - ssi_private->clk = devm_clk_get(&pdev->dev, NULL); + ssi_private->clk = devm_clk_get(&pdev->dev, "ipg"); if (IS_ERR(ssi_private->clk)) { ret = PTR_ERR(ssi_private->clk); - dev_err(&pdev->dev, "could not get clock: %d\n", ret); - return ret; - } - - ret = clk_prepare_enable(ssi_private->clk); - if (ret) { - dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); + dev_err(&pdev->dev, "could not get ipg clock: %d\n", ret); return ret; } @@ -1236,7 +1250,6 @@ static int fsl_ssi_imx_probe(struct platform_device *pdev, return 0; error_pcm: - clk_disable_unprepare(ssi_private->clk); return ret; } @@ -1246,7 +1259,6 @@ static void fsl_ssi_imx_clean(struct platform_device *pdev, { if (!ssi_private->use_dma) imx_pcm_fiq_exit(pdev); - clk_disable_unprepare(ssi_private->clk); } static int fsl_ssi_probe(struct platform_device *pdev) @@ -1321,7 +1333,11 @@ static int fsl_ssi_probe(struct platform_device *pdev) return -ENOMEM; } - ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem, + if (ssi_private->soc->imx) + ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev, + "ipg", iomem, &fsl_ssi_regconfig); + else + ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem, &fsl_ssi_regconfig); if (IS_ERR(ssi_private->regs)) { dev_err(&pdev->dev, "Failed to init register map\n");