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[RFC,v2,13/13] WIP: arm64: dts: qcom: qrb5165-rb5: add bus-pwrseq property to pcie0

Message ID 20210829131305.534417-14-dmitry.baryshkov@linaro.org (mailing list archive)
State RFC
Delegated to: Luiz Von Dentz
Headers show
Series create power sequencing subsystem | expand

Commit Message

Dmitry Baryshkov Aug. 29, 2021, 1:13 p.m. UTC 
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
index 326330f528fc..0c347cb6f8e0 100644
--- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
+++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
@@ -689,6 +689,7 @@  wifi-therm@1 {
 
 &pcie0 {
 	status = "okay";
+	bus-pwrseq = <&qca_pwrseq 0>;
 };
 
 &pcie0_phy {