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[35.185.214.157]) by smtp.gmail.com with ESMTPSA id a15-20020a170902eccf00b0016bf8048bd2sm7284130plh.175.2022.07.12.14.03.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 14:03:27 -0700 (PDT) From: Prashant Malani To: linux-kernel@vger.kernel.org, chrome-platform@lists.linux.dev Cc: bleung@chromium.org, heikki.krogerus@linux.intel.com, Prashant Malani , Guenter Roeck Subject: [PATCH 1/2] platform/chrome: cros_ec_typec: Rename port altmode array Date: Tue, 12 Jul 2022 21:03:17 +0000 Message-Id: <20220712210318.2671292-1-pmalani@chromium.org> X-Mailer: git-send-email 2.37.0.144.g8ac04bfd2-goog Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Rename "p_altmode" to "port_altmode" which is a less ambiguous name for the port_altmode struct array. Signed-off-by: Prashant Malani Acked-by: Heikki Krogerus --- drivers/platform/chrome/cros_ec_typec.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c index d6088ba447af..b9848e80f372 100644 --- a/drivers/platform/chrome/cros_ec_typec.c +++ b/drivers/platform/chrome/cros_ec_typec.c @@ -60,8 +60,7 @@ struct cros_typec_port { uint8_t mux_flags; uint8_t role; - /* Port alt modes. */ - struct typec_altmode p_altmode[CROS_EC_ALTMODE_MAX]; + struct typec_altmode port_altmode[CROS_EC_ALTMODE_MAX]; /* Flag indicating that PD partner discovery data parsing is completed. */ bool sop_disc_done; @@ -282,16 +281,16 @@ static void cros_typec_register_port_altmodes(struct cros_typec_data *typec, struct cros_typec_port *port = typec->ports[port_num]; /* All PD capable CrOS devices are assumed to support DP altmode. */ - port->p_altmode[CROS_EC_ALTMODE_DP].svid = USB_TYPEC_DP_SID; - port->p_altmode[CROS_EC_ALTMODE_DP].mode = USB_TYPEC_DP_MODE; + port->port_altmode[CROS_EC_ALTMODE_DP].svid = USB_TYPEC_DP_SID; + port->port_altmode[CROS_EC_ALTMODE_DP].mode = USB_TYPEC_DP_MODE; /* * Register TBT compatibility alt mode. The EC will not enter the mode * if it doesn't support it, so it's safe to register it unconditionally * here for now. */ - port->p_altmode[CROS_EC_ALTMODE_TBT].svid = USB_TYPEC_TBT_SID; - port->p_altmode[CROS_EC_ALTMODE_TBT].mode = TYPEC_ANY_MODE; + port->port_altmode[CROS_EC_ALTMODE_TBT].svid = USB_TYPEC_TBT_SID; + port->port_altmode[CROS_EC_ALTMODE_TBT].mode = TYPEC_ANY_MODE; port->state.alt = NULL; port->state.mode = TYPEC_STATE_USB; @@ -431,7 +430,7 @@ static int cros_typec_enable_tbt(struct cros_typec_data *typec, data.enter_vdo |= TBT_ENTER_MODE_ACTIVE_CABLE; if (!port->state.alt) { - port->state.alt = &port->p_altmode[CROS_EC_ALTMODE_TBT]; + port->state.alt = &port->port_altmode[CROS_EC_ALTMODE_TBT]; ret = cros_typec_usb_safe_state(port); if (ret) return ret; @@ -473,7 +472,7 @@ static int cros_typec_enable_dp(struct cros_typec_data *typec, /* Configuration VDO. */ dp_data.conf = DP_CONF_SET_PIN_ASSIGN(pd_ctrl->dp_mode); if (!port->state.alt) { - port->state.alt = &port->p_altmode[CROS_EC_ALTMODE_DP]; + port->state.alt = &port->port_altmode[CROS_EC_ALTMODE_DP]; ret = cros_typec_usb_safe_state(port); if (ret) return ret;