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[99.107.94.179]) by smtp.googlemail.com with ESMTPSA id k3-20020a0cabc3000000b0063d5d173a51sm611422qvb.50.2023.10.05.09.07.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 09:07:55 -0700 (PDT) From: "Dustin L. Howett" To: Benson Leung , Guenter Roeck , chrome-platform@lists.linux.dev, Kieran Levin , Mario Limonciello Cc: "Dustin L. Howett" Subject: [PATCH v1 3/4] cros_ec_lpc: add a quirks system, and propagate quirks from DMI Date: Thu, 5 Oct 2023 11:07:01 -0500 Message-ID: <20231005160701.19987-5-dustin@howett.net> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231005160701.19987-1-dustin@howett.net> References: <20231005160701.19987-1-dustin@howett.net> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Some devices ship a ChromeOS EC in a non-standard configuration; quirks allow cros_ec_lpc to account for these non-standard configurations. It supports the following quirks: - CROS_EC_LPC_QUIRK_REMAP_MEMORY: use a different port I/O base for MMIO to the EC's memory region - CROS_EC_LPC_QUIRK_SHORT_HOSTCMD_RESERVATION: only attempt to reserve 0xff (rather than 0x100) I/O ports for the host command region Signed-off-by: Dustin L. Howett --- drivers/platform/chrome/cros_ec_lpc.c | 41 ++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index ef7943e6a01d..c06575625d2f 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -34,6 +34,27 @@ /* True if ACPI device is present */ static bool cros_ec_lpc_acpi_device_found; +/* If this quirk is enabled, the driver will only reserve 0xFF I/O ports + * (rather than 0x100) for the host command mapped memory region. + */ +#define CROS_EC_LPC_QUIRK_SHORT_HOSTCMD_RESERVATION BIT(0) +/* If this quirk is enabled, lpc_driver_data.quirk_mmio_memory_base will be used + * as the base port for EC mapped memory. + */ +#define CROS_EC_LPC_QUIRK_REMAP_MEMORY BIT(1) + +/** + * struct lpc_driver_data - driver data attached to a DMI device ID to indicate + * hardware quirks. + * @quirks: a bitfield composed of quirks from CROS_EC_LPC_QUIRK_* + * @quirk_mmio_memory_base: The first I/O port addressing EC mapped memory (used + * when quirks (...REMAP_MEMORY) is set. + */ +struct lpc_driver_data { + u32 quirks; + u16 quirk_mmio_memory_base; +}; + /** * struct cros_ec_lpc - LPC device-specific data * @mmio_memory_base: The first I/O port addressing EC mapped memory. @@ -363,14 +384,32 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) acpi_status status; struct cros_ec_device *ec_dev; struct cros_ec_lpc *ec_lpc; + struct lpc_driver_data *driver_data; + int region1_size; u8 buf[2] = {}; int irq, ret; + u32 quirks = 0; ec_lpc = devm_kzalloc(dev, sizeof(*ec_lpc), GFP_KERNEL); if (!ec_lpc) return -ENOMEM; ec_lpc->mmio_memory_base = EC_LPC_ADDR_MEMMAP; + region1_size = EC_HOST_CMD_REGION_SIZE; + + driver_data = platform_get_drvdata(pdev); + if (driver_data) { + quirks = driver_data->quirks; + + if (quirks) + dev_warn(dev, "loaded with quirks %8.08x\n", quirks); + + if (quirks & CROS_EC_LPC_QUIRK_REMAP_MEMORY) + ec_lpc->mmio_memory_base = driver_data->quirk_mmio_memory_base; + + if (quirks & CROS_EC_LPC_QUIRK_SHORT_HOSTCMD_RESERVATION) + region1_size -= 1; + } /* * The Framework Laptop (and possibly other non-ChromeOS devices) @@ -420,7 +459,7 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) return -EBUSY; } if (!devm_request_region(dev, EC_HOST_CMD_REGION1, - EC_HOST_CMD_REGION_SIZE, dev_name(dev))) { + region1_size, dev_name(dev))) { dev_err(dev, "couldn't reserve region1\n"); return -EBUSY; }